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1. (WO2017095432) FORMING INTERCONNECTS WITH SELF-ASSEMBLED MONOLAYERS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/095432 International Application No.: PCT/US2015/063875
Publication Date: 08.06.2017 International Filing Date: 04.12.2015
IPC:
H01L 21/4763 (2006.01) ,H01L 21/31 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
34
the devices having semiconductor bodies not provided for in groups H01L21/06, H01L21/16, and H01L21/18159
46
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/36-H01L21/428142
461
to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
4763
Deposition of non-insulating-, e.g. conductive-, resistive-, layers on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054-1549, US
MAESTRE CARO, Aranzazu [ES/US]; US (US)
CHEBIAM, Ramanan V. [IN/US]; US (US)
Inventors:
MAESTRE CARO, Aranzazu; US
CHEBIAM, Ramanan V.; US
Agent:
GUPTA, Rishi; US
Priority Data:
Title (EN) FORMING INTERCONNECTS WITH SELF-ASSEMBLED MONOLAYERS
(FR) FORMATION D'INTERCONNEXIONS COMPRENANT DES MONOCOUCHES AUTO-ASSEMBLÉES
Abstract:
(EN) Embodiments of the disclosure are directed to using a SAM liner to promote electroless deposition of metal for integrated circuit interconnects. The SAM liner can be formed on a dielectric substrate. A protective layer can be formed on the SAM liner. The protective layer can double as a seed layer for electroless deposition of an interconnect metal. The interconnect metal can be deposited on the protective layer using electroless deposition. The dielectric, with the SAM liner, the protective layer, and the interconnect metal can be annealed to reflow the interconnect metal into trenches formed in the dielectric.
(FR) Selon des modes de réalisation, l'invention concerne l'utilisation d'une chemise en monocouche auto-assemblée (SAM) pour favoriser le dépôt autocatalytique de métal pour des interconnexions de circuit intégré. La chemise SAM peut être formée sur un substrat diélectrique. Une couche de protection peut être formée sur la chemise SAM. La couche de protection peut servir de couche de germe pour le dépôt autocatalytique d'un métal d'interconnexion. Le métal d'interconnexion peut être déposé sur la couche de protection au moyen d'un dépôt autocatalytique. Le diélectrique, avec la chemise SAM, la couche de protection et le métal d'interconnexion, peut être recuit pour refondre le métal d'interconnexion dans des tranchées formées dans le diélectrique.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
US20180323101