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1. (WO2017094682) SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SAME
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/094682 International Application No.: PCT/JP2016/085230
Publication Date: 08.06.2017 International Filing Date: 28.11.2016
IPC:
G09F 9/30 (2006.01) ,G02F 1/1368 (2006.01) ,G09F 9/00 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/786 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
30
in which the desired character or characters are formed by combining individual elements
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
吉田 徳生 YOSHIDA Tokuo; --
Agent:
奥田 誠司 OKUDA Seiji; JP
Priority Data:
2015-23455801.12.2015JP
Title (EN) SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SAME
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET PROCÉDÉ PERMETTANT DE FABRIQUER CE DERNIER
(JA) 半導体装置およびその製造方法
Abstract:
(EN) A semiconductor device is provided with a circuit including a first thin-film transistor (TFT) (101) that is an oxide semiconductor TFT, an inorganic insulating layer (11) covering the first TFT, a lower transparent electrode and an upper transparent electrode disposed with a dielectric layer (17) interposed therebetween, and a shield layer (30) formed from the same transparent conducting layer as the lower or upper transparent electrode. One of the lower and upper transparent electrodes is a common electrode, and the shield layer (30) is electrically connected to the common electrode. The shield layer (30) includes a second gate electrode (BG) of the first TFT, (a) the second gate (BG) being disposed on the inorganic insulating layer so as to be in contact with the upper surface of the inorganic insulating layer, or (b) in the channel area of the first TFT, the dielectric layer (17) being in contact with the upper surface of the inorganic insulating layer (11) and the second gate electrode (BG) being disposed on the dielectric layer so as to be in contact with the upper surface of the dielectric layer.
(FR) La présente invention concerne un dispositif à semi-conducteur qui comporte un circuit comprenant un premier transistor à couches minces (TFT pour Thin-Film Transistor) (101) qui est un transistor TFT à semi-conducteur à oxyde, une couche isolante inorganique (11) recouvrant le premier transistor TFT, une électrode transparente inférieure et une électrode transparente supérieure disposée avec une couche diélectrique (17) intercalée entre ces dernières et une couche de blindage (30) composée de la même couche conductrice transparente que celle de l'électrode transparente inférieure ou supérieure. L'une des électrodes transparentes inférieure et supérieure est une électrode commune et la couche de blindage (30) est raccordée électriquement à l'électrode commune. La couche de blindage (30) comprend une seconde électrode de grille (BG) du premier transistor TFT, (a) la seconde grille (BG) étant disposée sur la couche isolante inorganique de sorte à être en contact avec la surface supérieure de la couche isolante inorganique, ou (b) dans la zone de canal du premier transistor TFT, la couche diélectrique (17) étant en contact avec la surface supérieure de la couche isolante inorganique (11) et la seconde électrode de grille (BG) étant disposée sur la couche diélectrique de sorte à être en contact avec la surface supérieure de la couche diélectrique.
(JA) 半導体装置は、酸化物半導体TFTである第1のTFT(101)を含む回路と、第1のTFTを覆う無機絶縁層(11)と、誘電体層(17)を介して配置された下部透明電極および上部透明電極と、下部または上部透明電極と同じ透明導電膜から形成されたシールド層(30)とを備え、下部および上部透明電極の一方は共通電極であり、シールド層(30)は共通電極と電気的に接続されており、シールド層(30)は、第1のTFTの第2ゲート電極(BG)を含み、(a)第2ゲート電極(BG)は無機絶縁層上に、無機絶縁層の上面と接するように配置されている、あるいは、(b)第1のTFTのチャネル領域上において、誘電体層(17)は無機絶縁層(11)の上面と接しており、かつ、第2ゲート電極(BG)は誘電体層上に、誘電体層の上面と接するように配置されている。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
US20180374955