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1. (WO2017094339) SILICON CARBIDE SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/094339 International Application No.: PCT/JP2016/078902
Publication Date: 08.06.2017 International Filing Date: 29.09.2016
IPC:
H01L 29/78 (2006.01) ,H01L 29/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
Applicants:
三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 東京都千代田区丸の内二丁目7番3号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors:
田中 梨菜 TANAKA Rina; JP
福井 裕 FUKUI Yutaka; JP
菅原 勝俊 SUGAWARA Katsutoshi; JP
黒岩 丈晴 KUROIWA Takeharu; JP
香川 泰宏 KAGAWA Yasuhiro; JP
Agent:
吉竹 英俊 YOSHITAKE Hidetoshi; JP
有田 貴弘 ARITA Takahiro; JP
Priority Data:
2015-23637003.12.2015JP
Title (EN) SILICON CARBIDE SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR AU CARBURE DE SILICIUM
(JA) 炭化珪素半導体装置
Abstract:
(EN) The present invention relates to a silicon carbide semiconductor device that can suppress variations in on-current and variations in threshold values depending on the crystal surface. The silicon carbide semiconductor device comprises: a silicon carbide drift layer 2 formed on the top face of a silicon carbide semiconductor substrate 1 having an off-angle; a body region 5; a source region 3; a plurality of trenches 7; a gate insulating film 9; a gate electrode 10; a source electrode 11; a drain electrode 12, and a depletion suppressing layer 6. The depletion suppressing layer is positioned so as to be interposed between the plurality of trenches in a plan view, and in the direction in which the off-angle is provided on the silicon carbide semiconductor substrate, the distance between the depletion suppressing layer and one of the trenches that is adjacent to the depletion suppressing layer is different from the distance between the depletion suppressing layer and another of the trenches that is adjacent to the depletion suppressing layer.
(FR) La présente invention concerne un dispositif à semi-conducteur au carbure de silicium qui peut supprimer les variations du courant à l'état passant et les variations de valeurs de seuil en fonction de la surface cristalline. Le dispositif à semi-conducteur au carbure de silicium comprend : une couche de migration en carbure de silicium (2) formée sur la face supérieure d'un substrat semi-conducteur en carbure de silicium (1) présentant un angle de décalage ; une zone de corps (5) ; une zone de source (3) ; une pluralité de tranchées (7) ; un film d'isolation de grille (9) ; une électrode de grille (10) ; une électrode de source (11) ; une électrode de drain (12) ; et une couche de suppression d'appauvrissement (6). La couche de suppression d'appauvrissement est positionnée de manière à être intercalée entre la pluralité de tranchées en vue plane, et dans la direction dans laquelle l'angle de décalage est pratiqué sur le substrat semi-conducteur en carbure de silicium, la distance entre la couche de suppression d'appauvrissement et l'une des tranchées, qui est adjacente à la couche de suppression d'appauvrissement, est différente de la distance entre la couche de suppression d'appauvrissement et une autre des tranchées qui est adjacente à la couche de suppression d'appauvrissement.
(JA) 結晶面によるオン電流のばらつきおよびしきい値のばらつきを抑制することができる炭化珪素半導体装置に関する。炭化珪素半導体装置は、オフ角を有する炭化珪素半導体基板1の上面に形成される炭化珪素ドリフト層2と、ボディ領域5と、ソース領域3と、複数のトレンチ7と、ゲート絶縁膜9と、ゲート電極10と、ソース電極11と、ドレイン電極12と、空乏化抑制層6とを備える。空乏化抑制層は、平面視において複数のトレンチに挟まれて位置し、炭化珪素半導体基板のオフ角が付いた方向において、空乏化抑制層と空乏化抑制層に隣接する一方のトレンチとの間の距離が、空乏化抑制層と空乏化抑制層に隣接する他方のトレンチとの間の距離とは異なる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
CN108292680DE112016005558US20180358429