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1. (WO2017094189) SEMICONDUCTOR MODULE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/094189 International Application No.: PCT/JP2015/084164
Publication Date: 08.06.2017 International Filing Date: 04.12.2015
IPC:
H01L 23/02 (2006.01) ,H01L 25/07 (2006.01) ,H01L 25/18 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
02
Containers; Seals
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
Applicants:
三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 東京都千代田区丸の内二丁目7番3号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors:
大宅 大介 OYA Daisuke; JP
Agent:
吉竹 英俊 YOSHITAKE Hidetoshi; JP
Priority Data:
Title (EN) SEMICONDUCTOR MODULE
(FR) MODULE SEMI-CONDUCTEUR
(JA) 半導体モジュール
Abstract:
(EN) The purpose of the present invention is to provide a semiconductor module, wherein a case and a base plate are bonded to each other using a simple structure, and whereby breakdown strength can be improved. A semiconductor module of the present invention is provided with: a base plate 1; a semiconductor chip 2 that is disposed further toward the inner side than an outer peripheral portion of the base plate 1, said semiconductor chip being above the base plate 1; and a case 3, which is bonded to the outer peripheral portion of the base plate 1 using an adhesive 6, and which houses the semiconductor chip 2. An upper surface portion of the base plate 1 is provided with a recessed section or a protruding section, said upper surface portion being between the semiconductor chip 2 and an inner wall 3a of the case 3 in plan view.
(FR) La présente invention a pour objet de fournir un module semi-conducteur pour lequel un boîtier et une plaque de base sont reliés l'un à l'autre à l'aide d'une structure simple et de telle sorte que la résistance au claquage puisse être améliorée. Un module semi-conducteur de la présente invention comprend : une plaque de base (1) ; une puce à semi-conducteur (2) qui est disposée davantage vers le côté interne qu'une partie périphérique externe de la plaque de base (1), ladite puce à semi-conducteur se trouvant au-dessus de la plaque de base (1) ; et un boîtier (3), qui est relié à la partie périphérique externe de la plaque de base (1) à l'aide d'un adhésif (6), et qui loge la puce à semi-conducteur (2). Une partie de surface supérieure de la plaque de base (1) est pourvue d'une section renfoncée ou d'une section saillante, ladite partie de surface supérieure se trouvant entre la puce à semi-conducteur (2) et une paroi interne (3a) du boîtier (3) selon une vue en plan.
(JA) 簡素な構造でケース及びベース板を接合し、かつ絶縁耐量を高めることが可能な半導体モジュールを提供することを目的とする。半導体モジュールは、ベース板1と、ベース板1の外周部よりも内側でベース板1上方に配設された半導体チップ2と、ベース板1の外周部と接着剤6によって接合され、半導体チップ2を収容するケース3とを備える。ベース板1の上面のうち平面視でケース3の内壁3aと半導体チップ2との間の部分に、凹部または凸部が配設されている。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
JPWO2017094189CN108292631US20180286771DE112015007169