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1. (WO2017094180) POWER SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/094180 International Application No.: PCT/JP2015/084132
Publication Date: 08.06.2017 International Filing Date: 04.12.2015
IPC:
H01L 25/07 (2006.01) ,H01L 23/04 (2006.01) ,H01L 25/18 (2006.01) ,H05K 7/06 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
02
Containers; Seals
04
characterised by the shape
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
7
Constructional details common to different types of electric apparatus
02
Arrangements of circuit components or wiring on supporting structure
06
on insulating boards
Applicants:
三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 東京都千代田区丸の内二丁目7番3号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors:
荒木 翔子 ARAKI Shoko; JP
林田 幸昌 HAYASHIDA Yukimasa; JP
伊達 龍太郎 DATE Ryutaro; JP
Agent:
吉竹 英俊 YOSHITAKE Hidetoshi; JP
Priority Data:
Title (EN) POWER SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR DE PUISSANCE
(JA) パワー半導体装置
Abstract:
(EN) The purpose of the present invention is to provide a technology that offers margins in the arrangement, positional relationship, and size of constituent elements. A power semiconductor device is provided with: a substrate on which a semiconductor chip is disposed; an electrode 2 of which one end is fixed to the substrate and which is disposed upright with respect to the substrate; and an insulating case 3 which houses the electrode 2 and which includes a portion opposing the other end of the electrode 2. The power semiconductor device is also provided with an electrically conductive nut 4 inserted into the case 3 in said portion of the case 3, and an electrically conductive component which electrically connects the other end of the electrode 2 to the nut 4.
(FR) L'objet de la présente invention est de fournir une technologie qui offre des marges dans l'agencement, la relation de position, et la taille des éléments constitutifs. Un dispositif à semi-conducteur de puissance est pourvu : d'un substrat sur lequel est disposée une puce semi-conductrice ; d'une électrode 2 dont une extrémité est fixée au substrat et qui est placée verticalement par rapport au substrat ; et d'un boîtier isolant 3 qui renferme l'électrode 2 et qui comprend une partie opposée à l'autre extrémité de l'électrode 2. Le dispositif à semi-conducteur de puissance comprend également un écrou électroconducteur 4 inséré dans le boîtier 3 dans ladite partie du boîtier 3, et un composant électroconducteur qui connecte électriquement l'autre extrémité de l'électrode 2 et l'écrou 4.
(JA)  構成要素の配置、位置関係及び寸法に余裕を持たせることが可能な技術を提供することを目的とする。パワー半導体装置は、半導体チップが配設された基板と、一端が基板に固定され、基板に対し立設状に設けられた電極2と、電極2を収容し、電極2の他端に対向する部分を有する絶縁性のケース3と備える。また、パワー半導体装置は、ケース3の当該部分においてケース3に挿通された導電性のナット4と、電極2の他端とナット4とを電気的に接続する導電部品とを備える。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
JPWO2017094180CN108369943US20180261517DE112015007166