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1. (WO2017094132) COMPUTER AND METHOD FOR CONTROLLING COMPUTER
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/094132 International Application No.: PCT/JP2015/083846
Publication Date: 08.06.2017 International Filing Date: 02.12.2015
IPC:
G06F 9/48 (2006.01) ,G06F 9/46 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
46
Multiprogramming arrangements
48
Programme initiating; Programme switching, e.g. by interrupt
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
46
Multiprogramming arrangements
Applicants:
株式会社日立製作所 HITACHI, LTD. [JP/JP]; 東京都千代田区丸の内一丁目6番6号 6-6, Marunouchi 1-chome, Chiyoda-ku, Tokyo 1008280, JP
Inventors:
田口 学豊 TAGUCHI, Gakuho; JP
Agent:
特許業務法人ウィルフォート国際特許事務所 WILLFORT INTERNATIONAL PATENT FIRM; 東京都中央区日本橋小網町19-7 日本橋TCビル 1階 Nihonbashi TC Bldg. 1F, 19-7, Nihonbashi Koamicho, Chuo-ku, Tokyo 1030016, JP
Priority Data:
Title (EN) COMPUTER AND METHOD FOR CONTROLLING COMPUTER
(FR) ORDINATEUR ET PROCÉDÉ POUR COMMANDER UN ORDINATEUR
(JA) 計算機および計算機の制御方法
Abstract:
(EN) The computer 1 according to the present invention includes a plurality of physical processors 2, a hypervisor 10, and a virtual machine 11 controlled by the hypervisor. The virtual machine includes a virtual processor 12 and a guest program 13. The hypervisor produces a first physical processor that processes an external interruption in a first execution mode and a second physical processor that processes an external interruption in a second execution mode. The first physical processor has all received external interruptions processed by the guest program on the virtual processor allocated to the first physical processor. The second physical processor has all received external interruptions subjected to emulation processing by the hypervisor. The hypervisor controls whether an external interruption is destined to the first physical processor or the second physical processor.
(FR) La présente invention concerne un ordinateur (1) qui comprend une pluralité de processeurs physiques (2), un hyperviseur (10), et une machine virtuelle (11) commandée par l’hyperviseur. La machine virtuelle comprend un processeur virtuel (12) et un programme d’invité (13). L’hyperviseur produit un premier processeur physique qui traite une interruption externe dans un premier mode d’exécution et un second processeur physique qui traite une interruption externe dans un second mode d’exécution. Le premier processeur physique a toutes les interruptions externes reçues traitées par le programme d’invité sur le processeur virtuel attribué au premier processeur physique. Le second processeur physique a toutes les interruptions externes reçues soumises à un traitement d’émulation par l’hyperviseur. L’hyperviseur commande le point de savoir si l’interruption externe est destinée au premier processeur physique ou au second processeur physique.
(JA) 本発明の計算機1は、複数の物理プロセッサ2と、ハイパバイザ10と、ハイパバイザにより制御される仮想計算機11を備える。仮想計算機は、仮想プロセッサ12と、ゲストプログラム13とを含む。ハイパバイザは、第1実行モードで外部割込みを処理する第1物理プロセッサと、第2実行モードで外部割込みを処理する第2物理プロセッサとを生成する。第1物理プロセッサは、受け付けた全ての外部割込みを、第1物理プロセッサに割り当てられた仮想プロセッサ上のゲストプログラムにより処理させる。第2物理プロセッサは、受け付けた全ての外部割込みを、ハイパバイザでエミュレーション処理させる。ハイパバイザは、外部割込みの宛先を第1物理プロセッサまたは第2物理プロセッサのいずれにするかを制御する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)