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1. (WO2017093829) SEMICONDUCTOR ON INSULATOR SUBSTRATE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/093829 International Application No.: PCT/IB2016/056720
Publication Date: 08.06.2017 International Filing Date: 08.11.2016
IPC:
H01L 21/762 (2006.01) ,H01L 21/265 (2006.01) ,H01L 21/18 (2006.01) ,H01L 23/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
762
Dielectric regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
26
Bombardment with wave or particle radiation
263
with high-energy radiation
265
producing ion implantation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
Applicants:
THE SILANNA GROUP PTY LTD [AU/AU]; 37 Brandl Street Eight Mile Plains, Queensland 4113, AU
Inventors:
BRAWLEY, Andrew; AU
LIM, Gary; AU
IMTHURN, George; US
Priority Data:
62/263,50404.12.2015US
62/275,10305.01.2016US
Title (EN) SEMICONDUCTOR ON INSULATOR SUBSTRATE
(FR) SUBSTRAT SEMI-CONDUCTEUR SUR ISOLANT
Abstract:
(EN) Various semiconductor wafers and their methods of fabrication are disclosed. One exemplary process comprises, forming a layer consisting essentially of aluminum nitride on a first wafer. The first wafer includes a substrate. The process also comprises bonding a second wafer to the first wafer. The aluminum nitride layer is interposed between the substrate and the second wafer after the bonding step. The process also comprises separating the first and second wafers to form a semiconductor on insulator (SOI) wafer. The SOI receives a layer of semiconductor material from the second wafer during the separating step. The SOI wafer includes the layer of semiconductor material, the layer consisting essentially of aluminum nitride, and the substrate after the separating step.
(FR) L'invention concerne diverses tranches de semi-conducteur et leurs procédés de fabrication. Un procédé illustratif consiste à former une couche constituée essentiellement de nitrure d'aluminium sur une première tranche. La première tranche est un substrat. Le procédé consiste également à coller une seconde tranche sur la première tranche. Après l'étape de collage, la couche de nitrure d'aluminium est intercalée entre le substrat et la seconde tranche. Le procédé consiste également à séparer les première et seconde tranches afin de former une tranche semi-conducteur sur isolant (SOI). Pendant l'étape de séparation, la tranche SOI reçoit, de la seconde tranche, une couche de matériau semi-conducteur. Après l'étape de séparation, la tranche SOI comprend la couche de matériau semi-conducteur, la couche essentiellement constituée de nitrure d'aluminium et le substrat.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
US20180294158