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1. (WO2017092980) AMPLIFIER ARRANGEMENT AND SWITCHED CAPACITOR INTEGRATOR
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/092980 International Application No.: PCT/EP2016/076999
Publication Date: 08.06.2017 International Filing Date: 08.11.2016
IPC:
H03F 1/26 (2006.01) ,H03F 3/00 (2006.01) ,H03F 3/45 (2006.01) ,H03F 3/42 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
1
Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
26
Modifications of amplifiers to reduce influence of noise generated by amplifying elements
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
3
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
3
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
45
Differential amplifiers
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
3
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
42
Amplifiers with two or more amplifying elements having their dc paths in series with the load, the control electrode of each element being excited by at least part of the input signal, e.g. so-called totem-pole amplifiers
Applicants:
AMS AG [AT/AT]; Schloss Premstätten Tobelbader Str. 30 8141 Unterpremstätten, AT
Inventors:
STEINER, Matthias; AT
FITZI, Andreas; CH
Agent:
ASSOCIATION NO. 175; EPPING HERMANN FISCHER PATENTANWALTSGESELLSCHAFT MBH; Schloßschmidstr. 5 80639 München, DE
Priority Data:
15198050.504.12.2015EP
Title (EN) AMPLIFIER ARRANGEMENT AND SWITCHED CAPACITOR INTEGRATOR
(FR) MONTAGE AMPLIFICATEUR ET INTÉGRATEUR À CAPACITÉS COMMUTÉES
Abstract:
(EN) An amplifier arrangement has a first differential stage with a first transistor pair, a second differential stage with a first and a second transistor pair, each pair having a common source connection coupled to a drain terminal to a respective one of the transistors of the first differential stage. The amplifier arrangement further has a first complementary differential stage with a transistor pair having opposite conductivity type compared to the transistor pair of the first differential stage, and a second complementary differential stage with a first and a second transistor pair of the complementary conductivity type. The first and the second complementary differential stage are connected symmetrically compared to the first and the second differential stage. The transistors of the second complementary differential stage are symmetrically connected to the transistors of the second differential stage such that respective first, second, third and fourth current paths are formed. A pair of output terminals is coupled to the first and the fourth current path. Gate terminals of the transistors of each of the stages are coupled to a respective pair of input terminals.
(FR) L'invention concerne un montage amplificateur qui comprend un premier étage différentiel comportant une première paire de transistors, et un second étage différentiel comportant une première et une seconde paire de transistors, chaque paire ayant une connexion de source commune couplée à une borne de drain d'un transistor respectif des transistors du premier étage différentiel. Le montage amplificateur comprend en outre un premier étage différentiel complémentaire comportant une paire de transistors ayant un type de conductivité opposé par rapport à la paire de transistors du premier étage différentiel, et un second étage différentiel complémentaire comportant une première et une seconde paire de transistors du type de conductivité complémentaire. Le premier et le second étage différentiel complémentaire sont connectés symétriquement par rapport au premier et au second étage différentiel. Les transistors du second étage différentiel complémentaire sont connectés symétriquement aux transistors du second étage différentiel de manière à former des premier, deuxième, troisième et quatrième chemins de courant. Une paire de bornes de sortie sont couplées au premier et au quatrième chemin de courant. Des bornes de grille des transistors de chacun des étages sont couplées à une paire respective de bornes d'entrée.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
CN108702135US20190006998