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1. (WO2017092940) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH A SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/092940 International Application No.: PCT/EP2016/076085
Publication Date: 08.06.2017 International Filing Date: 28.10.2016
IPC:
H01L 21/336 (2006.01) ,H01L 29/78 (2006.01) ,H01L 29/739 (2006.01) ,H01L 29/10 (2006.01) ,H01L 29/16 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70
Bipolar devices
72
Transistor-type devices, i.e. able to continuously respond to applied control signals
739
controlled by field effect
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
10
with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
16
including, apart from doping materials or other impurities, only elements of the fourth group of the Periodic System in uncombined form
Applicants:
ABB SCHWEIZ AG [CH/CH]; Brown Boveri Strasse 6 5400 Baden, CH
Inventors:
BARTOLF, Holger; CH
RAHIMO, Munaf; CH
KNOLL, Lars; CH
MIHAILA, Andrei; CH
MINAMISAWA, Renato; CH
Agent:
ABB PATENT ATTORNEYS; Association 154, c/o ABB Schweiz AG, Intellectual Property CH-IP Brown Boveri Strasse 6 5400 Baden, CH
Priority Data:
15197558.802.12.2015EP
Title (EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH A SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET PROCÉDÉ DE FABRICATION DE CE DISPOSITIF À SEMI-CONDUCTEUR
Abstract:
(EN) A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product (10), (b) forming source regions (3, 3') by applying a first mask (34) with a first and second mask layer (35, 36) and applying an n dopant (31), forming a well layer (5) by removing such part of the first mask (34), which is arranged between the two source regions (3, 3'), and applying a p dopant (51), forming two channel regions (4, 4') by forming a third mask (46) by performing an etching step, by which the first mask layer (35) is farther removed at the openings than the second mask layer (36), and then removing the second mask layer (36), wherein the remaining first mask layer (35') forms a third mask (46),) and applying a p dopant (41), wherein a well layer depth (50) is at least as large as a channel layer depth (40), (c) after step (b) for forming a plug (6) applying a fourth mask, which covers the source regions (3, 3') and the channel layers (4, 4') and applying a p fourth dopant to a greater depth than the well layer depth (50) and with a higher doping concentration than the well layers (5, 5').
(FR) L'invention porte sur un procédé de fabrication d'un dispositif à semi-conducteur qui consiste : (a) à prendre un produit formant substrat à large bande interdite (10), (b) à former des zones de source (3, 3') par application d'un premier masque (34) ayant des première et deuxième couches de masque (35, 36) et par application d'un dopant n (31), à former une couche de puits (5) par élimination de la partie du premier masque (34) qui est disposée entre les deux zones de source (3, 3') et par application d'un dopant p (51), à former deux zones de canal (4, 4') par formation d'un troisième masque (46) par exécution d'une étape de gravure, par laquelle la première couche de masque (35) est éliminée au niveau des ouvertures plus loin que la deuxième couche de masque (36), puis par élimination de la deuxième couche de masque (36), la première couche de masque restante (35') formant un troisième masque (46), et par application d'un dopant p (41), une profondeur de couche de puits (50) étant au moins aussi grande qu'une profondeur de couche de canal (40), (c) après l'étape (b), pour former un bouchon (6), à appliquer un quatrième masque qui recouvre les zones de source (3, 3') et les couches de canal (4, 4') et à appliquer un quatrième dopant p à une profondeur supérieure à la profondeur de couche de puits (50) et avec une plus forte concentration de dopage que les couches de puits (5, 5').
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
EP3384523CN108604551IN201847021334