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1. (WO2017092459) SYSTEM ON CHIP SOC MONITORING METHOD, DEVICE AND COMPUTER STORAGE MEDIUM
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/092459 International Application No.: PCT/CN2016/098040
Publication Date: 08.06.2017 International Filing Date: 05.09.2016
IPC:
G01R 31/28 (2006.01)
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28
Testing of electronic circuits, e.g. by signal tracer
Applicants:
深圳市中兴微电子技术有限公司 SANECHIPS TECHNOLOGY CO., LTD. [CN/CN]; 中国广东省深圳市 南山区西丽街道留仙大道中兴工业园 ZTE Industrial Park, Liuxian Avenue, Xili Street, Nanshan District Shenzhen, Guangdong 518055, CN
Inventors:
邹飞 ZOU, Fei; CN
Agent:
北京派特恩知识产权代理有限公司 CHINA PAT INTELLECTUAL PROPERTY OFFICE; 中国北京市 海淀区海淀南路21号中关村知识产权大厦B座2层 2nd Floor, Zhongguancun Intellectual Property Building, Block B No.21 Haidian South Road, Haidian Beijing 100080, CN
Priority Data:
201510883827.604.12.2015CN
Title (EN) SYSTEM ON CHIP SOC MONITORING METHOD, DEVICE AND COMPUTER STORAGE MEDIUM
(FR) PROCÉDÉ DE SURVEILLANCE DE SYSTÈME SUR PUCE (SOC), DISPOSITIF ET SUPPORT DE STOCKAGE INFORMATIQUE
(ZH) 片上系统SOC的监控方法、装置和计算机存储介质
Abstract:
(EN) A System On Chip SOC monitoring method comprises: a node monitoring module monitors a bus access behavior of a monitored node in the SOC and obtains bus monitoring information of the monitored node (101); the node monitoring module sends the bus monitoring information and its own identification information as a bus monitoring result of the monitored node to a monitoring master control module through a serial communication link established by the node monitoring module and the monitoring master control module (102). By means of the above method, the position of an abnormal point that causes the bus access abnormality can be simply positioned.
(FR) La présente invention concerne un procédé de surveillance de système sur puce (SoC) qui comprend les étapes suivantes : un module de surveillance de nœud surveille un comportement d'accès de bus d'un nœud surveillé dans le SoC et obtient des informations de surveillance de bus du nœud surveillé (101); le module de surveillance de nœud envoie les informations de surveillance de bus et ses propres informations d'identification en tant que résultat de surveillance de bus du nœud surveillé à un module de commande maître de surveillance par l'intermédiaire d'une liaison de communication série établie par le module de surveillance de nœud et le module de commande maître de surveillance (102). Au moyen du procédé ci-dessus, la position d'un point anormal qui cause l'anomalie d'accès de bus peut-être localisée simplement.
(ZH) 一种片上系统SOC的监控方法,该方法包括:节点监控模块监测SOC内被监控节点的总线访问行为,获得被监控节点的总线监测信息(101);节点监控模块将总线监测信息、及自身的标识信息作为被监控节点的总线监测结果,通过节点监控模块与监控主控模块建立的串行通信链路,发送给监控主控模块(102)。通过上述方法,可以简单定位出导致总线访问异常的异常点的位置。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)