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1. (WO2017092142) MANUFACTURING METHOD FOR LOW-TEMPERATURE POLYSILICON TFT SUBSTRATE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/092142 International Application No.: PCT/CN2015/099985
Publication Date: 08.06.2017 International Filing Date: 30.12.2015
IPC:
H01L 21/84 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
84
the substrate being other than a semiconductor body, e.g. being an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
深圳市华星光电技术有限公司 SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国广东省深圳市 光明新区塘明大道9-2号 No.9-2, Tangming Road, Guangming District Shenzhen, Guangdong 518132, CN
Inventors:
李松杉 LI, Songshan; CN
Agent:
深圳市德力知识产权代理事务所 COMIPS INTELLECTUAL PROPERTY OFFICE; 中国广东省深圳市 福田区上步中路深勘大厦15E Room 15E Shenkan Building,Shangbu Zhong Road Shenzhen, Guangdong 518028, CN
Priority Data:
201510885433.403.12.2015CN
Title (EN) MANUFACTURING METHOD FOR LOW-TEMPERATURE POLYSILICON TFT SUBSTRATE
(FR) PROCÉDÉ DE PRODUCTION D'UN SUBSTRAT POUR TRANSISTOR À COUCHES MINCES EN SILICIUM POLYCRISTALLIN À BASSE TEMPÉRATURE
(ZH) 低温多晶硅TFT基板的制作方法
Abstract:
(EN) Provided is a manufacturing method for a low-temperature polysilicon TFT substrate. After N type heavily doped regions (31) are formed at two sides of a polysilicon layer (3), a first grid insulation layer (41), a first grid (51), a second grid insulation layer (42) and a second grid (52) are successively formed, wherein the width of the second grid (52) is greater than the width of the first grid (51), to prepare a low electric field region in the polysilicon layer (3), thereby reducing the effect of a leakage current; or the first grid (51) and the first grid insulation layer (41) are formed at first, the polysilicon layer (3) and the N type heavily doped regions (31) are formed on the first grid insulation layer (41), the second grid insulation layer (42) and the second grid (52) are formed then, the thickness of the second grid insulation layer (42) is greater than the thickness of the first grid insulation layer (41), the width of the second grid (52) is greater than the width of the first grid (51), so that the portion of the second grid (52) that exceeds the first grid (51) and the thickness of the second grid insulation layer (42) included in the polysilicon layer (3) are relatively thick, the generated electric field is smaller, and the effect of the leakage current is thus reduced. The technological process is simplified, and the production cost is reduced.
(FR) La présente invention concerne un procédé de production d'un substrat pour transistor à couches minces (TFT) en silicium polycristallin à basse température. Après la formation de régions fortement dopées de type N (31) sur les deux côtés d'une couche de silicium polycristallin (3), une première couche d'isolation (41) de grille, une première grille (51), une seconde couche d'isolation (42) de grille et une seconde grille (52) sont formées successivement, la largeur de la seconde grille (52) étant supérieure à la largeur de la première grille (51), pour préparer une région de faible champ électrique dans la couche de silicium polycristallin (3), réduisant ainsi l'effet d'un courant de fuite ; ou la première grille (51) et la première couche d'isolation (41) de grille sont formées dans un premier temps, la couche de silicium polycristallin (3) et les régions fortement dopées de type N (31) sont formées sur la première couche d'isolation (41) de grille, puis la seconde couche d'isolation (42) de grille et la seconde grille (52) sont formées, l'épaisseur de la seconde couche d'isolation (42) de grille étant supérieure à l'épaisseur de la première couche d'isolation (41) de grille, la largeur de la seconde grille (52) étant supérieure à la largeur de la première grille (51), de sorte que la partie de la seconde grille (52) qui dépasse la première grille (51) et l'épaisseur de la seconde couche d'isolation (42) de grille incluse dans la couche de silicium polycristallin (3) sont relativement épaisses, le champ électrique généré est plus faible et l'effet du courant de fuite est ainsi réduit. Le procédé technologique est simplifié et le coût de production est réduit.
(ZH) 提供一种低温多晶硅TFT基板的制作方法,在多晶硅层(3)两侧形成N型重掺杂区域(31)后,依次形成第一栅极绝缘层(41)、第一栅极(51)、第二栅极绝缘层(42)、第二栅极(52),且第二栅极(52)的宽度大于第一栅极(51)的宽度,以制作出多晶硅层(3)中的低电场区域,从而起到减小漏电流的作用;或者先形成第一栅极(51)、第一栅极绝缘层(41),在第一栅极绝缘层(41)上形成多晶硅层(3)及N型重掺杂区域(31),再形成第二栅极绝缘层(42)、第二栅极(52),且第二栅极绝缘层(42)的厚度大于第一栅极绝缘层(41)的厚度,第二栅极(52)的宽度大于第一栅极(51)的宽度,以使得第二栅极(52)超出第一栅极(51)的部分和多晶硅层(3)夹杂的第二栅极绝缘层(42)的厚度较厚,产生的电场较小,从而起到减小漏电流的作用;简化了工艺流程,降低了生产成本。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)
Also published as:
US20180033808