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1. (WO2017091780) 3D CROSS-POINT ARRAY AND PROCESS FLOWS
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/091780 International Application No.: PCT/US2016/063686
Publication Date: 01.06.2017 International Filing Date: 23.11.2016
IPC:
H01L 27/10 (2006.01) ,H01L 27/102 (2006.01) ,H01L 27/108 (2006.01) ,H01L 45/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
102
including bipolar components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
45
Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
Applicants:
HSU, Fu-Chang [US/US]; US
Inventors:
HSU, Fu-Chang; US
HSU, Fu-Chang; US
Agent:
JACKSON, Juneko; US
LEE, Otto O.; US
Priority Data:
62/260,30726.11.2015US
Title (EN) 3D CROSS-POINT ARRAY AND PROCESS FLOWS
(FR) MATRICE DE POINTS DE CONNEXION 3D ET FLUX DE TRAITEMENT
Abstract:
(EN) Three-dimensional cross-point array and process flows. In an exemplary embodiment, a method is provided that includes forming stacked layers, performing a first lithography operation on the stacked layers to form cell columns, and performing a second lithography operation on the stacked layers to form first vertical openings that are filled with first conductor layers to form one or more word line connections in a first direction. The method also includes performing a third lithography operation on the stacked layers to form second vertical openings that are filled with second conductor layers to form one or more bit line connections in a second direction.
(FR) L'invention concerne une matrice de points de connexion tridimensionnelle (3D) et des flux de traitement. Dans un mode de réalisation, un procédé est décrit qui consiste à former des couches empilées, à effectuer une première opération de lithographie sur les couches empilées pour former des colonnes de cellules, et à effectuer une deuxième opération de lithographie sur les couches empilées pour former des premières ouvertures verticales qui sont remplies avec des premières couches conductrices afin de former une ou plusieurs connexions de ligne de mot dans une première direction. Le procédé consiste également à effectuer une troisième opération de lithographie sur les couches empilées pour former des deuxièmes ouvertures verticales qui sont remplies avec des deuxièmes couches conductrices afin de former une ou plusieurs connexions de ligne de bit dans une deuxième direction.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)