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1. (WO2017090584) THIN FILM TRANSISTOR, OXIDE SEMICONDUCTOR FILM AND SPUTTERING TARGET
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/090584 International Application No.: PCT/JP2016/084539
Publication Date: 01.06.2017 International Filing Date: 22.11.2016
IPC:
H01L 29/786 (2006.01) ,C23C 14/08 (2006.01) ,C23C 14/34 (2006.01) ,H01L 21/203 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
14
Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
06
characterised by the coating material
08
Oxides
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
14
Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
22
characterised by the process of coating
34
Sputtering
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
203
using physical deposition, e.g. vacuum deposition, sputtering
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
株式会社アルバック ULVAC, INC. [JP/JP]; 神奈川県茅ヶ崎市萩園2500番地 2500 Hagisono, Chigasaki-shi, Kanagawa 2538543, JP
Inventors:
上野 充 UENO, Mitsuru; JP
清田 淳也 KIYOTA, Junya; JP
小林 大士 KOBAYASHI, Motoshi; JP
武井 応樹 TAKEI, Masaki; JP
高橋 一寿 TAKAHASHI, Kazutoshi; JP
日高 浩二 HIDAKA, Koji; JP
川越 裕 KAWAGOE, Yuu; JP
武末 健太郎 TAKESUE, Kentarou; JP
和田 優 WADA, Masaru; JP
Agent:
大森 純一 OMORI, Junichi; JP
Priority Data:
2015-22938025.11.2015JP
Title (EN) THIN FILM TRANSISTOR, OXIDE SEMICONDUCTOR FILM AND SPUTTERING TARGET
(FR) TRANSISTOR À COUCHES MINCES, COUCHE SEMI-CONDUCTRICE D'OXYDE ET CIBLE DE PULVÉRISATION
(JA) 薄膜トランジスタ、酸化物半導体膜及びスパッタリングターゲット
Abstract:
(EN) A thin film transistor according to one mode of the present invention is provided with the following: a gate electrode; an active layer constituted from an oxide containing indium, zinc and titanium; a gate insulating film formed between the gate electrode and the active layer; and a source electrode and drain electrode that are electrically connected to the active layer. The atomic proportions of each element relative to the total quantity of indium, zinc and titanium that constitute the oxide are 24-80 at.% of indium, 16-70 at.% of zinc and 0.1-20 at.% of titanium.
(FR) L'invention concerne, dans l'un de ses modes de réalisation, un transistor à couches minces comprenant les éléments suivants : une électrode de grille ; une couche active constituée à partir d'un oxyde contenant de l'indium, du zinc et du titane ; une couche mince d'isolation de grille formée entre l'électrode de grille et la couche active ; et une électrode de source et une électrode de drain qui sont connectées électriquement à la couche active. Les proportions atomiques de chaque élément par rapport à la quantité totale d'indium, de zinc et de titane qui constituent cet oxyde, sont de 24 à 80 % at d'indium, de 16 à 70 % at de zinc et de 0,1 à 20 % at titane.
(JA) 本発明の一形態に係る薄膜トランジスタは、ゲート電極と、インジウム、亜鉛及びチタンを含む酸化物で構成された活性層と、上記ゲート電極と上記活性層との間に形成されたゲート絶縁膜と、上記活性層と電気的に接続されるソース電極及びドレイン電極とを具備する。上記酸化物を構成するインジウム、亜鉛及びチタンの合計量に占める各元素の原子比は、インジウムが24原子%以上80原子%以下、亜鉛が16原子%以上70原子%以下、チタンが0.1原子%以上20原子%以下である。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
KR1020180057678CN108352410US20180337285