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1. (WO2017090477) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/090477 International Application No.: PCT/JP2016/083688
Publication Date: 01.06.2017 International Filing Date: 14.11.2016
IPC:
H01L 29/786 (2006.01) ,G02F 1/1343 (2006.01) ,G02F 1/1368 (2006.01) ,G09F 9/30 (2006.01) ,H01L 21/28 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/41 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
1333
Constructional arrangements
1343
Electrodes
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
30
in which the desired character or characters are formed by combining individual elements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
内田 誠一 UCHIDA Seiichi; --
岡田 訓明 OKADA Kuniaki; --
Agent:
奥田 誠司 OKUDA Seiji; JP
Priority Data:
2015-22861624.11.2015JP
Title (EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET PROCÉDÉ DE FABRICATION DE DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置および半導体装置の製造方法
Abstract:
(EN) A semiconductor device (1001) provided with: a thin-film transistor (101) having an oxide semiconductor layer (16) that includes a channel region, and a source contact region and a drain contact region disposed respectively on both sides of the channel region; an insulating layer that is disposed so as to cover the oxide semiconductor layer (16) and that has a contact hole (CH) from which the drain contact region is exposed; and a transparent electrode (24) that is in contact with the drain contact region in the contact hole (CH). At least a part R of the drain contact region overlaps a gate electrode (12) as viewed from a direction normal to a substrate. In an arbitrarily defined cross section of at least the part (R) of the drain contact region along the channel width direction, the width of the oxide semiconductor layer (16) is larger than the width of the gate electrode (12), and the gate electrode (12) is covered with the oxide semiconductor layer (16), with a gate insulating layer interposed therebetween.
(FR) L'invention concerne un dispositif à semi-conducteur (1001) comprenant : un transistor à couches minces (101) comportant une couche d'oxyde semi-conducteur (16) qui comprend une zone de canal, et une zone de contact de source et une zone de contact de drain disposées respectivement des deux côtés de la zone de canal ; une couche isolante qui est disposée de manière à recouvrir la couche d'oxyde semi-conducteur (16) et qui comporte un trou de contact (CH) par lequel la zone de contact de drain est apparente ; et une électrode transparente (24) qui est en contact avec la zone de contact de drain dans le trou de contact (CH). Au moins une partie R de la zone de contact de drain chevauche une électrode de grille (12) vue dans une direction perpendiculaire à un substrat. Dans une section transversale arbitrairement définie d'au moins la partie (R) de la zone de contact de drain dans le sens de la largeur du canal, la largeur de la couche d'oxyde semi-conducteur (16) est plus grande que la largeur de l'électrode de grille (12), et l'électrode de grille (12) est recouverte par la couche d'oxyde semi-conducteur (16), une couche d'isolation de grille étant intercalée entre ces dernières.
(JA) 半導体装置(1001)は、チャネル領域とチャネル領域の両側にそれぞれ配置されたソースコンタクト領域およびドレインコンタクト領域とを含む酸化物半導体層(16)を有する薄膜トランジスタ(101)と、酸化物半導体層(16)を覆うように配置され、ドレインコンタクト領域を露出するコンタクトホール(CH)を有する絶縁層と、コンタクトホール(CH)内でドレインコンタクト領域と接する透明電極(24)とを備え、基板の法線方向から見たとき、ドレインコンタクト領域の少なくとも一部Rは、ゲート電極(12)と重なっており、ドレインコンタクト領域の少なくとも一部(R)をチャネル幅方向に横切る任意の断面において、酸化物半導体層(16)の幅はゲート電極(12)の幅よりも大きく、かつ、ゲート電極(12)は、ゲート絶縁層を介して酸化物半導体層(16)で覆われている。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)
Also published as:
CN108292685US20180358469