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1. (WO2017090183) SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/090183 International Application No.: PCT/JP2015/083404
Publication Date: 01.06.2017 International Filing Date: 27.11.2015
IPC:
H01L 29/06 (2006.01) ,H01L 29/41 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants:
サンケン電気株式会社 SANKEN ELECTRIC CO., LTD. [JP/JP]; 埼玉県新座市北野3丁目6番3号 6-3, Kitano 3-chome, Niiza-shi, Saitama 3528666, JP
Inventors:
大森 寛将 OMORI, Tomoyuki; JP
Agent:
三好 秀和 MIYOSHI, Hidekazu; JP
Priority Data:
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEURS
(JA) 半導体装置
Abstract:
(EN) The present invention is provided with: a first-conductivity-type first semiconductor region; second-conductivity-type second semiconductor regions which are arrayed apart from each other in the first semiconductor region so that a pn junction is formed between each of the second semiconductor regions and the first semiconductor region, and which stretch into a stripe pattern so that a super junction structure is formed in which the pn junctions are periodically arranged; a first main electrode which is arranged on the first main surface side of the first semiconductor region; a second main electrode which is arranged, in an element region, on the second main surface side of the first semiconductor region; a terminal electrode which is arranged at the outer edge of an outer periphery region on the second main surface side and which is electrically connected to the first main electrode; an insulating layer which is arranged, on the second main surface side, between the second main electrode and the terminal electrode; and a plurality of conductors which are arrayed apart from each other in the insulating layer, wherein the second main electrode and the terminal electrode are capacitively coupled by a capacitor group obtained by capacitors formed between the conductors being connected in series.
(FR) La présente invention comprend : une première zone semi-conductrice d'un premier type de conductivité ; des secondes zones semi-conductrices d'un second type de conductivité qui sont alignées à distance l'une de l'autre dans la première zone semi-conductrice de manière à former une jonction pn entre chacune des secondes zones semi-conductrices et la première zone semi-conductrice, et qui s'étendent en un motif de bandes de manière à former une structure de super-jonction dans laquelle les jonctions pn sont agencées périodiquement ; une première électrode principale qui est agencée côté première surface principale de la première zone semi-conductrice ; une seconde électrode principale qui est agencée, dans une zone d'élément, côté seconde surface principale de la première zone semi-conductrice ; une électrode de borne qui est agencée au niveau du bord extérieur d'une zone périphérique extérieure côté seconde surface principale et qui est connectée électriquement à la première électrode principale ; une couche isolante qui est agencée, côté seconde surface principale, entre la seconde électrode principale et l'électrode de borne ; et une pluralité de conducteurs qui sont alignés à distance l'un de l'autre dans la couche isolante, la seconde électrode principale et l'électrode de borne étant couplées de manière capacitive par un groupe de condensateurs obtenu par connexion en série de condensateurs formés entre les conducteurs.
(JA)  第1導電型の第1の半導体領域と、第1の半導体領域との間にpn接合をそれぞれ形成するように第1の半導体領域の内部に互いに離間して配列され、pn接合が周期的に配置されたスーパージャンクション構造を構成するようにストライプ状に延伸する第2導電型の第2の半導体領域と、第1の半導体領域の第1主面側に配置された第1の主電極と、第1の半導体領域の第2主面側で素子領域に配置された第2の主電極と、第2主面側の外周領域の外縁に配置され、第1の主電極と電気的に接続された終端電極と、第2の主電極と終端電極との間で第2主面側に配置された絶縁層と、絶縁層の内部に互いに離間して配列された複数の導電体とを備え、導電体の間に形成されるコンデンサを直列接続したコンデンサ群によって第2の主電極と終端電極とが容量結合される。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)