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1. (WO2017069948) REGISTER COMMUNICATION IN A NETWORK-ON-A-CHIP ARCHITECTURE
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Pub. No.: WO/2017/069948 International Application No.: PCT/US2016/055402
Publication Date: 27.04.2017 International Filing Date: 05.10.2016
IPC:
G06F 9/30 (2006.01) ,G06F 9/302 (2006.01) ,G06F 9/318 (2006.01) ,G06F 9/32 (2006.01) ,G06F 9/34 (2006.01) ,G06F 9/38 (2006.01) ,G06F 9/44 (2006.01) ,G06F 12/08 (2016.01) ,G06F 15/16 (2006.01) ,G06F 15/78 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
302
Controlling the executing of arithmetic operations
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
318
with operation extension or modification
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
32
Address formation of the next instruction, e.g. incrementing the instruction counter, jump
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
34
Addressing or accessing the instruction operand or the result
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
38
Concurrent instruction execution, e.g. pipeline, look ahead
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
44
Arrangements for executing specific programmes
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
08
in hierarchically structured memory systems, e.g. virtual memory systems
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
15
Digital computers in general; Data processing equipment in general
16
Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
15
Digital computers in general; Data processing equipment in general
76
Architectures of general purpose stored programme computers
78
comprising a single central processing unit
Applicants: KNUEDGE, INC.[US/US]; 10350 Science Center Drive Suite 140 San Diego, California 92121, US
Inventors: PALMER, Douglas A.; US
WHITE, Andrew; US
Agent: BARZILAY, Ilan N.; US
Priority Data:
14/921,37723.10.2015US
Title (EN) REGISTER COMMUNICATION IN A NETWORK-ON-A-CHIP ARCHITECTURE
(FR) COMMUNICATION DE REGISTRE DANS UNE ARCHITECTURE DE RÉSEAU SUR PUCE
Abstract:
(EN) A network on a chip processor uses uniform addressing for both conventional memory and operand registers. The processor contains a large number of processing elements (e.g., 256). Each processing element has a number (e.g., 200) of operand registers to which it has direct, high-speed (e.g., single clock-cycle) access. Each of these operand registers is also assigned a global memory address, so other processing elements can read or write those operand registers as if they were located in main memory. Software that expects communication between processing elements to happen via memory can use memory-based reads/writes, but gain substantial speed by writing that data directly to the operand registers used for execution of instructions by the target processor.
(FR) Un registre sur un processeur de puce utilise un adressage uniforme pour la mémoire conventionnelle et les registres d'opérandes. Le processeur contient un grand nombre d'éléments de traitement (par exemple, 256). Chaque élément de traitement comprend un certain nombre (par exemple, 200) de registres d'opérandes auxquels il peut accéder directement et à grande vitesse (par exemple, un seul cycle d'horloge). Chacun de ces registres d'opérandes se voit également attribuer une adresse de mémoire globale afin que les autres éléments de traitement puissent lire ou écrire ces registres d'opérandes comme s'ils étaient situés dans la mémoire principale. Un logiciel qui attend qu'une communication survienne entre des éléments de traitement par le biais de la mémoire peut utiliser des lectures/écritures à base de mémoire, mais gagne considérablement en vitesse en écrivant ces données directement dans les registres d'opérandes utilisés pour l'exécution des instructions par le processeur cible.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)