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1. (WO2017069102) PROTECTIVE TAPE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
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Pub. No.: WO/2017/069102 International Application No.: PCT/JP2016/080777
Publication Date: 27.04.2017 International Filing Date: 18.10.2016
Chapter 2 Demand Filed: 17.08.2017
IPC:
H01L 21/304 (2006.01) ,H01L 21/301 (2006.01) ,H01L 21/56 (2006.01) ,H01L 21/60 (2006.01) ,H01L 21/683 (2006.01) ,H01L 23/29 (2006.01) ,H01L 23/31 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
304
Mechanical treatment, e.g. grinding, polishing, cutting
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
301
to subdivide a semiconductor body into separate parts, e.g. making partitions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67
Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
683
for supporting or gripping
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
29
characterised by the material
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
31
characterised by the arrangement
Applicants:
デクセリアルズ株式会社 DEXERIALS CORPORATION [JP/JP]; 東京都品川区大崎1丁目11番2号 ゲートシティ大崎イーストタワー8階 Gate City Osaki, East Tower 8F, 1-11-2, Osaki, Shinagawa-ku, Tokyo 1410032, JP
Inventors:
森山 浩伸 MORIYAMA, Hironobu; JP
Agent:
野口 信博 NOGUCHI, Nobuhiro; JP
Priority Data:
2015-20564719.10.2015JP
Title (EN) PROTECTIVE TAPE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
(FR) RUBAN PROTECTEUR ET PROCÉDÉ DE PRODUCTION DE DISPOSITIF SEMI-CONDUCTEUR
(JA) 保護テープ、及び半導体装置の製造方法
Abstract:
(EN) The purpose of the present invention is to suppress wafer chipping and to improve solder bonding qualities when mounting a semiconductor chip. The present invention includes: a step for affixing a protective tape 10 onto a wafer 21 surface on which bump electrodes 22 are formed, the protective tape having an adhesive layer 11, a thermoplastic resin layer 12, and a substrate film layer 13 in that order; a step for grinding a surface of the wafer 21 opposite the surface to which the protective tape 10 has been affixed; a step for affixing an adhesive tape 30 to the ground surface of the wafer 21; a step for peeling off the protective tape 10 so as to leave the adhesive layer 11 and remove other layers; a step for dicing the wafer 21 to which the adhesive tape 30 has been affixed to obtain individual semiconductor chips; and a step for curing the adhesive layer 11 before dicing. The storage shear modulus of the adhesive layer 11 after curing is 3.0E+08Pa-5.0E+09Pa, and the ratio of the height of the bump electrodes 22 to the thickness of the adhesive layer 11 of the protective tape 10 before affixing (thickness of the adhesive layer before affixing/height of the bump electrodes) is 1/30-1/6.
(FR) L'objet de la présente invention est de supprimer l'écaillage de tranche et d'améliorer des qualités de liaison par soudure lors du montage d'une puce semi-conductrice. La présente invention comprend : une étape consistant à fixer un ruban protecteur (10) sur une surface de tranche (21) sur laquelle sont formées des électrodes à protubérance (22), le ruban protecteur comprenant, dans cet ordre, une couche adhésive (11), une couche de résine thermoplastique (12) et une couche de film substrat (13) ; une étape consistant à broyer une surface de la tranche (21) opposée à la surface sur laquelle a été fixé le ruban protecteur (10) ; une étape consistant à fixer un ruban adhésif (30) sur la surface inférieure de la tranche (21) ; une étape consistant à détacher le ruban protecteur (10) de sorte à laisser la couche adhésive (11) et enlever d'autres couches ; une étape de découpage en dés de la tranche (21) sur laquelle a été fixé le ruban adhésif (30) afin d'obtenir des puces semi-conductrices individuelles ; ainsi qu'une étape consistant à durcir la couche adhésive (11) avant le découpage en dés. Le module de cisaillement au stockage de la couche adhésive (11) après durcissement est de 3,0E+08Pa-5,0E+09Pa et le rapport hauteur des électrodes à protubérance (22) - épaisseur de la couche adhésive (11) du ruban adhésif (10) avant fixation (épaisseur de la couche adhésive avant fixation/hauteur des électrodes à protubérance) est de 1/30-1/6.
(JA) ウエハのチッピングを抑制するとともに、半導体チップの実装時におけるはんだ接合性を良好にする。 突起電極22が形成されたウエハ21面に、接着剤層11と、熱可塑性樹脂層12と、基材フィルム層13とをこの順で有する保護テープ10を貼付する工程と、ウエハ21の保護テープ10貼付面の反対面をグラインドする工程と、ウエハ21のグラインド面に粘着テープ30を貼付する工程と、接着剤層11を残して保護テープ10を剥離し、他の層を除去する工程と、粘着テープ30が貼付されたウエハ21をダイシングし、個片の半導体チップを得る工程と、ダイシングの前に接着剤層11を硬化させる工程とを有し、硬化後の接着剤層11の貯蔵剪断弾性率が3.0E+08Pa~5.0E+09Paであり、貼付前の保護テープ10の接着剤層11の厚さと突起電極22の高さとの比(貼付前の接着剤層の厚さ/突起電極の高さ)が1/30~1/6である。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)