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1. (WO2017066341) MULTI-DIE PACKAGE COMPRISING UNIT SPECIFIC ALIGNMENT AND UNIT SPECIFIC ROUTING

Pub. No.:    WO/2017/066341    International Application No.:    PCT/US2016/056670
Publication Date: Fri Apr 21 01:59:59 CEST 2017 International Filing Date: Thu Oct 13 01:59:59 CEST 2016
IPC: H01L 21/768
Applicants: DECA TECHNOLOGIES INC.
Inventors: BISHOP, Craig
Title: MULTI-DIE PACKAGE COMPRISING UNIT SPECIFIC ALIGNMENT AND UNIT SPECIFIC ROUTING
Abstract:
A method of making a semiconductor device can include forming an embedded die panel by encapsulating a first semiconductor die and a second semiconductor die with conductive interconnects in a single step. An actual position of the first semiconductor die and second semiconductor die can be measured within the embedded die panel. The first semiconductor die and the second semiconductor die can be interconnected by a build-up interconnect structure comprising a first unit specific alignment portion aligned with the first semiconductor die, a second unit specific alignment portion aligned with the second semiconductor die, unit specific routing connecting the first unit specific alignment portion and the second unit specific alignment portion, and a fixed portion aligned with outline of embedded die panel and coupled to the unit specific routing.