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1. (WO2017065938) METHOD OF FORMING MEMORY ARRAY AND LOGIC DEVICES
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Pub. No.: WO/2017/065938 International Application No.: PCT/US2016/052517
Publication Date: 20.04.2017 International Filing Date: 19.09.2016
IPC:
H01L 21/02 (2006.01) ,H01L 21/8229 (2006.01) ,H01L 21/8239 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8222
Bipolar technology
8229
Memory structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
Applicants: SILICON STORAGE TECHNOLOGY, INC.[US/US]; 450 Holger Way San Jose, CA 95134, US
Inventors: KIM, Jinho; US
SU, Chien-sheng; US
ZHOU, Feng; US
LIU, Xian; US
DO, Nhan; US
TUNTASOOD, Prateep; US
GHAZAVI, Parviz; US
Agent: LIMBACH, Alan, A.; US
Priority Data:
15/264,45713.09.2016US
62/240,38912.10.2015US
Title (EN) METHOD OF FORMING MEMORY ARRAY AND LOGIC DEVICES
(FR) PROCÉDÉ DE FORMATION D'UNE MATRICE MÉMOIRE ET DISPOSITIFS LOGIQUES
Abstract:
(EN) A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas.
(FR) L'invention concerne un procédé de formation d'un dispositif de mémoire sur un substrat ayant des zones de mémoire, de noyau et de dispositif HV. Le procédé consiste à former une paire de couches conductrices dans les trois zones, à former une couche isolante sur les couches conductrices dans les trois zones (pour protéger les zones de noyau et de dispositif HV), puis à graver à travers la couche isolante et la paire de couches conductrices dans la zone de mémoire pour former des paquets de mémoires. Le procédé consiste en outre à former une couche isolante sur les paquets de mémoires (pour protéger la zone de mémoire), à retirer la paire de couches conductrices dans les zones de noyau et de dispositif HV, et à former des grilles conductrices disposées au-dessus du substrat et isolées de celui-ci dans les zones de noyau et de dispositif HV.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)