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1. (WO2017061194) WIRING STRUCTURE AND METHOD FOR PRODUCING WIRING STRUCTURE
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Pub. No.: WO/2017/061194 International Application No.: PCT/JP2016/075681
Publication Date: 13.04.2017 International Filing Date: 01.09.2016
IPC:
H01L 23/14 (2006.01) ,H01L 21/288 (2006.01) ,H01L 21/3205 (2006.01) ,H01L 21/768 (2006.01) ,H01L 23/12 (2006.01) ,H01L 23/32 (2006.01) ,H01L 23/522 (2006.01) ,H05K 1/11 (2006.01) ,H05K 3/40 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
14
characterised by the material or its electrical properties
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
283
Deposition of conductive or insulating materials for electrodes
288
from a liquid, e.g. electrolytic deposition
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
32
Holders for supporting the complete device in operation, i.e. detachable fixtures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
11
Printed elements for providing electric connections to or between printed circuits
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
40
Forming printed elements for providing electric connections to or between printed circuits
Applicants:
浜松ホトニクス株式会社 HAMAMATSU PHOTONICS K.K. [JP/JP]; 静岡県浜松市東区市野町1126番地の1 1126-1, Ichino-cho, Higashi-ku, Hamamatsu-shi, Shizuoka 4358558, JP
Inventors:
村松 雅治 MURAMATSU Masaharu; JP
鈴木 久則 SUZUKI Hisanori; JP
米田 康人 YONETA Yasuhito; JP
大塚 慎也 OTSUKA Shinya; JP
高橋 弘孝 TAKAHASHI Hirotaka; JP
Agent:
長谷川 芳樹 HASEGAWA Yoshiki; JP
黒木 義樹 KUROKI Yoshiki; JP
柴山 健一 SHIBAYAMA Kenichi; JP
Priority Data:
2015-19752005.10.2015JP
Title (EN) WIRING STRUCTURE AND METHOD FOR PRODUCING WIRING STRUCTURE
(FR) STRUCTURE DE CÂBLAGE, ET PROCÉDÉ DE FABRICATION DE CELLE-CI
(JA) 配線構造体、及び配線構造体の製造方法
Abstract:
(EN) This wiring structure is a wiring structure provided with a wiring pattern including a through-wiring pattern, the wiring structure comprising: a silicon substrate having a through hole in which the through-wiring pattern is arranged; an insulating layer provided at least along the wiring pattern and provided on a surface of the silicon substrate including the inner surface of the through hole; a boron layer provided on the insulating layer along the wiring pattern; and a metal layer provided on the boron layer.
(FR) L’invention concerne une structure de câblage dans laquelle est agencé un motif de câblage contenant un motif de câblage traversant, et qui est équipée : d’un substrat de silicium qui possède un trou traversant dans lequel est disposé le motif de câblage traversant ; d’une couche isolante qui se trouve au moins le long du motif de câblage, et qui est agencée à la surface du substrat de silicium contenant une face interne du trou traversant ; d’une couche de bore le long du motif de câblage, et agencée sur la couche isolante ; et d’une couche métallique agencée sur la couche de bore.
(JA) 配線構造体は、貫通配線パターンを含む配線パターンが設けられた配線構造体であって、貫通配線パターンが配置された貫通孔を有するシリコン基板と、少なくとも配線パターンに沿って、貫通孔の内面を含むシリコン基板の表面に設けられた絶縁層と、配線パターンに沿って絶縁層上に設けられたボロン層と、ボロン層上に設けられた金属層と、備える。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)