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1. (WO2017059781) PACKAGING METHOD AND PACKAGE STRUCTURE FOR IMAGE SENSING CHIP
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Pub. No.: WO/2017/059781 International Application No.: PCT/CN2016/100817
Publication Date: 13.04.2017 International Filing Date: 29.09.2016
IPC:
H01L 23/488 (2006.01) ,H01L 21/60 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60
Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
Applicants: CHINA WAFER LEVEL CSP CO., LTD.[CN/CN]; No. 29 Tinglan Lane SIP. Suzhou, Jiangsu 215026, CN
Inventors: WANG, Zhiqi; CN
WANG, Zhuowei; CN
XIE, Guoliang; CN
Agent: UNITALEN ATTORNEYS AT LAW; 7th Floor, Scitech Place No. 22, Jian Guo Men Wai Ave. Chao Yang District Beijing 100004, CN
Priority Data:
201510650103.710.10.2015CN
201520780135.410.10.2015CN
Title (EN) PACKAGING METHOD AND PACKAGE STRUCTURE FOR IMAGE SENSING CHIP
(FR) PROCÉDÉ D’ENCAPSULATION METTANT EN OEUVRE DES PUCES DE CAPTEUR D'IMAGE ET STRUCTURE D’ENCAPSULATION
(ZH) 影像传感芯片的封装方法以及封装结构
Abstract:
(EN) Provided are a packaging method and package structure for an image sensing chip. The method comprises: providing a wafer (100) having a first surface (101) and a second surface (102) opposite to the first surface (101), wherein the wafer (100) has multiple imaging sensing chips (110) arranged as a grid, the image sensing chip (110) has an image sensing region (111) and a solder pad (112), and the image sensing region (111) and the solder pad (112) are located at the side of the first surface (101) of the wafer (100); forming, at the second surface (102) of the wafer (100), an opening (113) extending towards the first surface (101), wherein the opening (113) exposes the solder pad (112); forming, at the second surface (102) of the wafer (100), a V-shaped cut recess (103) extending towards the first surface (101); and coating a photosensitive ink (117) on the second surface (102) of the wafer (100), such that the photosensitive ink (117) fills the V-shaped cut recess (103) and covers the opening (113), and a cavity (119) is formed between the opening (113) and the photosensitive ink (117). By forming the cavity (119) between the opening (113) and the photosensitive ink (117), the present invention effectively prevents separation of a wiring layer (115) from the solder pad (112), thereby improving the package yield rate of image sensing chips, and enhancing the reliability of the image sensing chip package structure.
(FR) L’invention a trait à un procédé d’encapsulation mettant en oeuvre des puces de capteur d'image et à une structure d’encapsulation, le procédé d’encapsulation consistant à : fournir une tranche (100) qui présente une première surface (101) ainsi qu’une seconde surface (102) en regard de la première surface (101), la tranche (100) présentant en outre une pluralité de puces de capteur d'image (110) qui présentent, à leur tour, des régions de capteur d’image (111) et un support envers de soudure (112), les régions de capteur d’image (111) et le support envers de soudure (112) se trouvant disposés sur un côté de la première surface (101) de la tranche (100) ; former sur la seconde surface (102) de la tranche (100) un orifice ouvert (113) s’étendant vers la première surface (101), l’orifice ouvert (113) laissant voir le support envers de soudure (112) ; former une cannelure incisive en forme de V (103) s’étendant en direction de la première surface (101) ; et revêtir la seconde surface (102) de la tranche (100) d’une encre photosensible (117) de telle sorte que l’encre photosensible (117) remplisse l’orifice ouvert (113) et forme une cavité (119) entre l’orifice ouvert (113) et l'encre photosensible (117) de manière à éviter de façon efficace qu’une couche de câblage (115) ne se détache du support envers de soudure, ce qui a pour effet d’améliorer la qualité de l’encapsulation des puces de capteur d’image et d’augmenter la fiabilité de la structure d'encapsulation des puces de capteur d’image.
(ZH) 提供一种影像传感芯片的封装方法以及封装结构,包括:提供晶圆(100),具有第一表面(101)以及与所述第一表面(101)相背的第二表面(102),所述晶圆(100)具有多颗网格排布的影像传感芯片(110),具有影像传感区(111)以及焊垫(112),所述影像传感区(111)以及焊垫(112)位于所述晶圆(100)的第一表面(101)侧;于所述晶圆(100)的第二表面(102)形成朝向第一表面(101)延伸的开孔(113),所述开孔(113)暴露出所述焊垫(112);于所述晶圆(100)的第二表面(102)形成朝向第一表面(101)延伸的V型切割槽(103);在所述晶圆(100)第二表面(102)涂布感光油墨(117),使感光油墨(117)充满所述V型切割槽(103),且所述感光油墨(117)覆盖所述开孔(113),并在所述开孔(113)与所述感光油墨(117)之间形成空腔(119),通过在开孔(113)与感光油墨(117)之间形成空腔(119),有效避免再布线层(115)与焊垫(112)脱离的情况,提升了影像传感芯片的封装良率,提高了影像传感芯片封装结构的信赖性。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)