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1. (WO2017059104) ADIABATIC PHASE GATES IN PARITY-BASED QUANTUM COMPUTERS

Pub. No.:    WO/2017/059104    International Application No.:    PCT/US2016/054495
Publication Date: Fri Apr 07 01:59:59 CEST 2017 International Filing Date: Fri Sep 30 01:59:59 CEST 2016
IPC: G06N 99/00
H01L 49/00
Applicants: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventors: CLARKE, David
SAU, Jay Deep
SARMA, Sankar Das
Title: ADIABATIC PHASE GATES IN PARITY-BASED QUANTUM COMPUTERS
Abstract:
Example methods and mechanisms are described herein for implementing and adiabatically operating a topological quantum computing (TQC) phase gate that complements the existing Clifford operations, and thereby allows universal quantum computation with Majorana systems. Further embodiments include a testing system for the phase gate that is feasible with Majorana zero modes and demonstrates violations of the CHSH-Bell inequality. Further, the design used for the testing of the inequality leads directly to a practical platform for performing universal TQC with Majorana wires in which explicit braiding need never occur. Thus, certain embodiments of the disclosed technology involve three synergistically connected aspects of anyonic TQC (in the context of the currently active area of using MZMs for topological quantum computation): a practical phase gate for universal topological quantum computation using MZMs, a precise protocol (using CHSH inequality) for testing that the desired gate operation has been achieved, and bypassing the necessity of MZM braiding (and so avoiding, e.g., problems of nonadiabaticity in the braids).