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1. (WO2017058422) CAPACITIVE COUPLING OF INTEGRATED CIRCUIT DIE COMPONENTS
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Pub. No.: WO/2017/058422 International Application No.: PCT/US2016/048889
Publication Date: 06.04.2017 International Filing Date: 26.08.2016
IPC:
H01L 23/522 (2006.01) ,H01L 23/50 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
50
for integrated circuit devices
Applicants: INVENSAS CORPORATION[US/US]; 3025 Orchard Parkway San Jose, CA 95134, US
Inventors: SITARAM, Arkalgud, R.; US
HABA, Belgacem; US
Agent: LATTIN, Christopher, W.; US
Priority Data:
15/247,70525.08.2016US
62/234,02228.09.2015US
Title (EN) CAPACITIVE COUPLING OF INTEGRATED CIRCUIT DIE COMPONENTS
(FR) COUPLAGE CAPACITIF DE COMPOSANTS DE PUCES DE CIRCUIT INTÉGRÉ
Abstract:
(EN) Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. An ultrathin layer of dielectric is formed on at least one surface to be coupled. When the two components, e.g., one from each die, are permanently contacted together, the ultrathin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive areas of each respective component. The ultrathin layer of dielectric may be composed of multiple layers of various dielectrics, but in one implementation, the overall thickness is less than approximately 50 nanometers. The capacitance per unit area of the capacitive interface formed depends on the particular dielectric constants κ of the dielectric materials employed in the ultrathin layer and their respective thicknesses. Electrical and grounding connections can be made at the edge of the coupled stack.
(FR) L'invention concerne le couplage capacitif de composants de puces de circuit intégré et d'autres zones conductrices. Chaque composant devant être couplé présente une surface comprenant au moins une zone conductrice, tel qu'un plot ou une plaque métallique. Une couche ultramince de diélectrique est formée sur au moins une surface devant être couplée. Lorsque les deux composants, par exemple l'une de chaque puce, sont en permanence en contact l'un avec l'autre, la couche ultramince de diélectrique reste entre les deux surfaces, en formant ainsi un condensateur ou une interface capacitive entre les zones conductrices de chaque composant respective. La couche ultramince de diélectrique peut se composer de multiples couches de divers diélectriques mais, dans un mode de réalisation, l'épaisseur totale est inférieure à environ 50 nanomètres. La capacité par unité de surface de l'interface capacitive formée dépend des constantes diélectriques κ particulières des matériaux diélectriques utilisés dans la couche ultramince et de leurs épaisseurs respectives. Des connexions électriques et de mise à la terre peuvent être réalisées sur le bord de l'empilement pile couplé.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)