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1. (WO2017057423) SURFACE MOUNT TYPE LC DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2017/057423    International Application No.:    PCT/JP2016/078553
Publication Date: 06.04.2017 International Filing Date: 28.09.2016
IPC:
H01F 27/00 (2006.01), H01F 17/00 (2006.01), H01G 4/40 (2006.01), H01L 21/822 (2006.01), H01L 27/04 (2006.01), H03H 7/01 (2006.01)
Applicants: MURATA MANUFACTURING CO., LTD. [JP/JP]; 10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto 6178555 (JP)
Inventors: ISHIZUKA, Kenichi; (JP).
YAZAKI, Hirokazu; (JP)
Agent: KAEDE PATENT ATTORNEYS' OFFICE; 1-4-34, Noninbashi, Chuo-ku, Osaka-shi, Osaka 5400011 (JP)
Priority Data:
2015-196393 02.10.2015 JP
Title (EN) SURFACE MOUNT TYPE LC DEVICE
(FR) DISPOSITIF LC DE TYPE MONTÉ EN SURFACE
(JA) 表面実装型LCデバイス
Abstract: front page image
(EN)This surface mount type LC device has: a substrate (10) having a first surface (S1); a plurality of inductors formed on the first surface (S1) of the substrate (10) and each configured by coil-shaped conductor patterns (70A, 70B, 70C, 70D); a first insulating layer (21) for covering the plurality of coil-shaped conductor patterns (70A, 70B, 70C, 70D); and a capacitor formed on top of the first insulating layer (21) and configured by planar electrodes. The planar electrodes cover first regions which are adjacent to each other and for which the current directions have a reverse relationship among the plurality of coil-shaped conductor patterns (70A, 70B, 70C, 70D) as seen in a plan view of the substrate (10).
(FR)La présente invention concerne un dispositif LC de type monté en surface qui comporte : un substrat (10) comportant une première surface (S1) ; une pluralité d’inductances formées sur la première surface (S1) du substrat (10) et constituées chacune de motifs conducteurs en forme de bobines (70A, 70B, 70C, 70D) ; une première couche isolante (21) qui recouvre la pluralité de motifs conducteurs en forme de bobines (70A, 70B, 70C, 70D) ; et un condensateur formé en haut de la première couche isolante (21) et constitué d’électrodes planaires. Les électrodes planaires recouvrent de premières zones qui sont adjacentes entre elles et pour lesquelles les directions de courant présentent une relation inverse parmi la pluralité de motifs conducteurs en forme de bobines (70A, 70B, 70C, 70D) en vue planaire du substrat (10).
(JA)表面実装型LCデバイスは、第1面(S1)を有する基板(10)と、基板(10)の第1面(S1)に形成された、それぞれコイル状導体パターン(70A,70B,70C,70D)で構成された複数のインダクタと、複数のコイル状導体パターン(70A,70B,70C,70D)を覆う第1絶縁層(21)と、第1絶縁層(21)の上部に形成された、面状電極によって構成されたキャパシタと、を有し、面状電極は、基板(10)の平面視で、複数のコイル状導体パターン(70A,70B,70C,70D)のうち、互いに近接し且つ電流方向が互いに逆関係にある第1領域を覆う。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)