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1. (WO2017041339) METHOD FOR PREPARING SUBSTRATE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/041339 International Application No.: PCT/CN2015/091471
Publication Date: 16.03.2017 International Filing Date: 08.10.2015
IPC:
H01L 21/02 (2006.01) ,H01L 21/31 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
Applicants:
深圳市华星光电技术有限公司 SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国广东省深圳市 光明新区塘明大道9-2号 No.9-2, Tangming Road, Guangming New District Shenzhen, Guangdong 518132, CN
武汉华星光电技术有限公司 WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国湖北省武汉市 东湖开发区高新大道666号生物城C5栋 Building C5, Biolake of Optics Valley, No.666 Gaoxin Avenue, East Lake High-tech Development Zone Wuhan, Hubei 430070, CN
Inventors:
李子健 LI, Zijian; CN
Agent:
北京聿宏知识产权代理有限公司 YUHONG INTELLECTUAL PROPERTY LAW FIRM; 中国北京市 西城区宣武门外大街6号庄胜广场第一座西翼713室吴大建刘华联 WU Dajian/LIU Hualian West Wing, Suite 713, One Junefield Plaza, 6 Xuanwumenwai Street, Xicheng District Beijing 100052, CN
Priority Data:
201510573490.910.09.2015CN
Title (EN) METHOD FOR PREPARING SUBSTRATE
(FR) PROCÉDÉ DE PRÉPARATION DE SUBSTRAT
(ZH) 基板制备方法
Abstract:
(EN) Provided is a method for preparing a substrate, comprising the following steps: step I. depositing an amorphous silicon layer (12) on a base material (11); step II. depositing a silicon dioxide layer (17) having a first thickness (D1) on the amorphous silicon layer (12); and step III. etching the silicon dioxide layer (17) until the thickness (D1) thereof is reduced to a second thickness (D2). According to the method, the silicon dioxide layer (17) having a required thickness can be prepared on the amorphous silicon layer (12). When an excimer laser annealing is performed, the prepared silicon dioxide layer (17) can sufficiently suppress protuberance at the crystal boundary of a polycrystalline silicon layer (18), thereby enabling the roughness of a prepared semiconductor layer to be decreased.
(FR) L'invention concerne un procédé de préparation d'un substrat, comprenant les étapes suivantes : étape I. déposer une couche de silicium amorphe (12) sur un matériau de base (11) ; étape II. déposer une couche de dioxyde de silicium (17) ayant une première épaisseur (D1) sur la couche de silicium amorphe (12) ; et étape III. graver la couche de dioxyde de silicium (17) jusqu'à ce que son épaisseur (D1) soit réduite à une seconde épaisseur (D2). Selon le procédé, la couche de dioxyde de silicium (17) ayant une épaisseur requise peut être préparée sur la couche de silicium amorphe (12). Lorsqu'un recuit au laser à excimère est effectué, la couche de dioxyde de silicium (17) préparée peut suffisamment supprimer la protubérance au niveau du contour cristallin d'une couche de silicium polycristallin (18), ce qui permet de diminuer la rugosité d'une couche semi-conductrice préparée.
(ZH) 一种基板制备方法,包括以下步骤:步骤一,在基材(11)上沉积非晶硅层(12),步骤二,在所述非晶硅层(12)上沉积第一厚度(D1)的二氧化硅层(17),步骤三,刻蚀所述二氧化硅层(17),直到其厚度(D1)降低到第二厚度(D2)。根据该方法,能够在非晶硅层(12)上制备所需厚度的二氧化硅层(17)。在进行准分子激光退火时,所制备的二氧化硅层(17)足以抑制多晶硅层(18)晶界处的隆起,使得所制备的半导体层的粗糙度较低。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)