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1. (WO2017041098) EMBEDDED SIGE PROCESS FOR MULTI-THRESHOLD PMOS TRANSISTORS

Pub. No.:    WO/2017/041098    International Application No.:    PCT/US2016/050409
Publication Date: Fri Mar 10 00:59:59 CET 2017 International Filing Date: Wed Sep 07 01:59:59 CEST 2016
IPC: H01L 27/06
H01L 21/8232
Applicants: TEXAS INSTRUMENTS INCORPORATED
TEXAS INSTRUMENTS JAPAN LIMITED
Inventors: CHOI, Younsung
RILEY, Deborah, J.
Title: EMBEDDED SIGE PROCESS FOR MULTI-THRESHOLD PMOS TRANSISTORS
Abstract:
In described examples of an integrated circuit and method having a first PMOS transistor (205) with extension (210) and pocket implants (212) and with SiGe source and drains (230) and having a second PMOS transistor (215) without extension and without pocket implants and with SiGe source and drains (230), the distance (C2Gd) from the SiGe source and drains (230) to the gate of the first PMOS transistor (205) is greater than the distance (C2Gu) from the SiGe source and drains (230) to the gate of the second PMOS transistor (215), and the turn on voltage of the first PMOS transistor (205) is at least 50 mV higher than the turn on voltage of the second PMOS transistor (215).