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1. (WO2017040172) METHOD AND APPARATUS FOR MITIGATING PARASITIC COUPLING IN A PACKAGED INTEGRATED CIRCUIT
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Pub. No.: WO/2017/040172 International Application No.: PCT/US2016/048568
Publication Date: 09.03.2017 International Filing Date: 25.08.2016
Chapter 2 Demand Filed: 28.03.2017
IPC:
H01L 21/48 (2006.01) ,H01L 23/552 (2006.01) ,H01L 23/495 (2006.01) ,H01L 23/66 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
48
Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/06-H01L21/326201
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
552
Protection against radiation, e.g. light
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
495
Lead-frames
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
64
Impedance arrangements
66
High-frequency adaptations
Applicants:
ANOKIWAVE, INC. [US/US]; 12555 High Bluff Drive San Diego, CA 92130, US
Inventors:
JAIN, Vipul; US
KINAYMAN, Noyan; US
ESMALI, Amir; US
MENON, Gaurav; US
JAIN, Nitin; US
Agent:
SUNSTEIN, Bruce D.; US
MURPHY, Timothy, M.; US
ASHER, Robert, M.; US
KLAYMAN, Jeffrey, T.; US
Priority Data:
14/846,09204.09.2015US
Title (EN) METHOD AND APPARATUS FOR MITIGATING PARASITIC COUPLING IN A PACKAGED INTEGRATED CIRCUIT
(FR) PROCÉDÉ ET APPAREIL D'ATTÉNUATION DE COUPLAGE PARASITE DANS UN CIRCUIT INTÉGRÉ SOUS BOÎTIER
Abstract:
(EN) A packaged IC has a package with a die paddle, a signal lead, and a ground lead. The packaged IC also has a die, secured to the package, with a ground pad and a signal pad. The signal pad is electrically connected to the signal lead, and the ground pad is electrically connected to both the die paddle and the ground lead.
(FR) L'invention concerne un circuit intégré (CI) sous boîtier, comprenant un boîtier pourvu d'une patte de puce, d'un conducteur de signal et d'un conducteur de masse. Le CI sous boîtier comprend également une puce fixée au boîtier, pourvue d'un plot de masse et d'un plot de signal. Le plot de signal est connecté électriquement au conducteur de signal, et le plot de masse est connecté électriquement à la patte de puce et au conducteur de masse.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)