A check bit read mode enables a memory device to provide internal check bits to an associated host. A memory controller of a memory subsystem can generate one or more read commands for memory devices of the memory subsystem. The read command can include address location information. The memory devices include memory arrays with memory locations addressable with the address location information. The memory locations have associated data and internal check bits, where the check bits are generated internally by the memory for error correction. If the memory device is configured for check bit read mode, in response to the read command, it sends the internal check bits associated with the identified address location. If the memory device is not configured check bit read mode, it returns the data in response to the read command without exposing the internal check bits.