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1. (WO2017039868) ELECTRONIC PACKAGE WITH CORNER SUPPORTS
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/039868 International Application No.: PCT/US2016/043405
Publication Date: 09.03.2017 International Filing Date: 21.07.2016
IPC:
H01L 23/00 (2006.01) ,H01L 21/56 (2006.01) ,H01L 23/31 (2006.01) ,H01L 23/488 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
31
characterised by the arrangement
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
Applicants:
PENMECHA, Bharat P. [IN/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
PENMECHA, Bharat P.; US
DUBEY, Manish; US
DIAS, Rajendra C.; US
BICEN, Baris; US
RAORANE, Digvijay; US
Agent:
PERDOK, Monique M.; US
WOO, Justin N., Reg. No. 62,686; US
SCHEER, Bradley W., Reg. No. 47,059; US
GOULD, James R., Reg. No. 72,086; US
MCCRACKIN, Ann M., Reg. No. 42,858; US
BLACK, David W., Reg. No. 42,331; US
BIANCHI, Timothy E., Reg. No. 39,610; US
BEEKMAN, Marvin L., Reg. No. 38,377; US
ARORA, Suneel, Reg. No. 42,267; US
Priority Data:
14/841,05231.08.2015US
Title (EN) ELECTRONIC PACKAGE WITH CORNER SUPPORTS
(FR) BOÎTIER ÉLECTRONIQUE À SUPPORTS DE COIN
Abstract:
(EN) Some example forms relate to an electronic package. The electronic package includes a substrate and a die attached to the substrate. A plurality of supports attached to the substrate adjacent to the die. At least one support in the plurality of supports is positioned adjacent to at least one corner of the die such that the at least one corner of the die is positioned adjacent to the at least one support. Other example forms relate to a method of fabricating an electronic package. The method includes securing a die to a substrate and securing a plurality of supports to the substrate such that at least one support is adjacent to at least one corner of the die.
(FR) Selon certains exemples de modes de réalisation, l'invention concerne un boîtier électronique. Le boîtier électronique comprend un substrat et une puce fixée au substrat. Une pluralité de supports sont fixés au substrat en position adjacente à la puce. Au moins un support de la pluralité de supports est positionné adjacent à au moins un coin de la puce de manière que l'au moins un coin de la puce soit positionné adjacent à l'au moins un support. Selon d'autres exemples de modes de réalisation, l'invention concerne un procédé de fabrication d'un boîtier électronique. Le procédé comprend les étapes consistant à fixer une puce à un substrat et à fixer une pluralité de supports au substrat de manière qu'au moins un support soit adjacent à au moins un coin de la puce.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)