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1. (WO2017039864) COMPILER OPTIMIZATION TO REDUCE THE CONTROL FLOW DIVERGENCE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/039864 International Application No.: PCT/US2016/043339
Publication Date: 09.03.2017 International Filing Date: 21.07.2016
IPC:
G06T 1/20 (2006.01) ,G06T 1/60 (2006.01) ,G06T 5/00 (2006.01) ,G06T 7/00 (2017.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
T
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
1
General purpose image data processing
20
Processor architectures; Processor configuration, e.g. pipelining
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
T
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
1
General purpose image data processing
60
Memory management
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
T
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
5
Image enhancement or restoration, e.g. from bit-mapped to bit-mapped creating a similar image
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
T
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
7
Image analysis, e.g. from bit-mapped to non bit-mapped
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
SATHE, Rahul P.; US
Agent:
MALLIE, Michael J.; US
HAMILTON, Howard S.; US
BERNADICOU, Michael A.; US
VINCENT, Lester J.; US
Priority Data:
14/843,69802.09.2015US
Title (EN) COMPILER OPTIMIZATION TO REDUCE THE CONTROL FLOW DIVERGENCE
(FR) OPTIMISATION DE COMPILATEUR POUR RÉDUIRE LA DIVERGENCE D'UN FLUX DE COMMANDE
Abstract:
(EN) In one embodiment a graphics processing system comprises a graphics processor having execution logic and shared memory and a shader compiler unit to compile a shader program for execution by the execution logic of the graphic processor, wherein the shader is to optimize the shader program during the compile, wherein to optimize the shader program includes to convert a divergent block of parallel instructions into a divergent block and a non-divergent block of instructions.
(FR) Dans un mode de réalisation, un système de traitement graphique comprend un processeur graphique ayant une logique d'exécution et une mémoire partagée, ainsi qu’une unité de compilateur de nuanceur permettant de compiler un programme de nuanceur afin qu'il soit exécuté par la logique d'exécution du processeur graphique, le nuanceur étant conçu pour optimiser le programme du nuanceur pendant la compilation et consistant, pour optimiser le programme du nuanceur, à convertir un bloc divergent d’instructions parallèles en un bloc divergent et un bloc non divergent d'instructions.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)