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1. (WO2017039856) BIASING CIRCUIT FOR LEVEL SHIFTER WITH ISOLATION
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/039856 International Application No.: PCT/US2016/042909
Publication Date: 09.03.2017 International Filing Date: 19.07.2016
IPC:
G05F 3/20 (2006.01) ,H03K 3/012 (2006.01) ,H03K 19/0175 (2006.01)
G PHYSICS
05
CONTROLLING; REGULATING
F
SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
3
Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
02
Regulating voltage or current
08
wherein the variable is dc
10
using uncontrolled devices with non-linear characteristics
16
being semiconductor devices
20
using diode-transistor combinations
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
3
Circuits for generating electric pulses; Monostable, bistable or multistable circuits
01
Details
012
Modifications of generator to improve response time or to decrease power consumption
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
19
Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
0175
Coupling arrangements; Interface arrangements
Applicants:
CYPRESS SEMICONDUCTOR CORPORATION [US/US]; 198 Champion Court San Jose, California 95134, US
Inventors:
GRADINARIU, Iulian C.; US
ASHOKKUMAR, Jayant; US
RAGHAVAN, Vijay; US
SAMSON, Bogdan; US
Priority Data:
14/965,73810.12.2015US
62/212,23731.08.2015US
Title (EN) BIASING CIRCUIT FOR LEVEL SHIFTER WITH ISOLATION
(FR) CIRCUIT DE POLARISATION POUR DISPOSITIF DE DÉCALAGE DE NIVEAU AVEC ISOLEMENT
Abstract:
(EN) A circuit includes a biasing circuit that includes a diode stack coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a transistor, a timer component and a current source. An input of the timer component is coupled to receive an isolation signal. The current source is configured to inject current for a period of time into the diode stack in response to a transition of the ISO signal between a high voltage and a low voltage. The biasing circuit also includes circuitry to generate an isolation delayed (ISO_DEL) signal. The ISO_DEL signal has a high voltage in response to the biasing signal being within a first threshold level and the ISO_DEL signal has a low voltage in response to the biasing signal being within a second threshold level. The biasing circuit outputs the ISO_DEL signal.
(FR) L'invention porte sur un circuit, qui comprend un circuit de polarisation comprenant un empilement de diodes couplé à un premier nœud. Le circuit de polarisation peut délivrer en sortie un signal de polarisation sur le premier nœud. Le circuit de polarisation comprend également un transistor, un composant temporisateur et une source de courant. Une entrée du composant temporisateur est couplée pour recevoir un signal d'isolement (ISO). La source de courant est configurée pour injecter un courant pendant une période de temps dans l'empilement de diodes en réponse à une transition du signal ISO entre une tension haute et une tension basse. Le circuit de polarisation comprend également un circuit pour générer un signal d'isolement retardé (ISO_DEL). Le signal ISO_DEL a une tension haute en réponse au fait que le signal de polarisation est en-deçà d'un premier niveau de seuil et le signal ISO_DEL a une tension basse en réponse au fait que le signal de polarisation est en-deçà d'un second niveau de seuil. Le circuit de polarisation délivre en sortie le signal ISO_DEL.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)