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1. (WO2017039854) METHOD FOR FABRICATING FERROELECTRIC RANDOM-ACCESS MEMORY ON PRE-PATTERNED BOTTOM ELECTRODE AND OXIDATION BARRIER

Pub. No.:    WO/2017/039854    International Application No.:    PCT/US2016/042849
Publication Date: Fri Mar 10 00:59:59 CET 2017 International Filing Date: Tue Jul 19 01:59:59 CEST 2016
IPC: H01L 27/108
Applicants: CYPRESS SEMICONDUCTOR CORPORATION
Inventors: SUN, Shan
Title: METHOD FOR FABRICATING FERROELECTRIC RANDOM-ACCESS MEMORY ON PRE-PATTERNED BOTTOM ELECTRODE AND OXIDATION BARRIER
Abstract:
Structure and method of fabrication of F-RAM cells are described. The F-RAM cell include ferroelectric capacitors forming over and with a pre-patterned barrier structure which has a planarized/chemically and/or mechanically polished top surface. The pre-patterned barrier structure includes multiple oxygen barriers having a structure of a bottom electrode layer over an oxygen barrier layer. The bottom electrode layer forms at least a part of the bottom electrode of the ferroelectric capacitor formed thereon.