Search International and National Patent Collections

1. (WO2017039852) DESKEW OF RISING AND FALLING SIGNAL EDGES

Pub. No.:    WO/2017/039852    International Application No.:    PCT/US2016/042742
Publication Date: Fri Mar 10 00:59:59 CET 2017 International Filing Date: Tue Jul 19 01:59:59 CEST 2016
IPC: H03K 5/1252
H03K 5/12
H03K 5/135
Applicants: TERADYNE, INC.
Inventors: VAN DER WAGT, Jan, Paul, Antonie
SARTSCHEV, Ronald, A.
PHILLIPS, Bradley, A.
Title: DESKEW OF RISING AND FALLING SIGNAL EDGES
Abstract:
Example circuitry includes: a first sampling circuit configured to operate based on a first clock signal, to receive data, and to sample the data, where the first clock signal is calibrated to compensate for a first timing error in a rising edge of the data; a second sampling circuit configured to operate based on a second clock signal, to receive the data, and to sample the data, where the second first clock signal is calibrated to compensate for a second timing error in a falling edge of the data; and a third sampling circuit to receive the data and a third clock signal, to sample the data based on the third clock signal to produce sampled data, and to control an output of the circuitry based on the sampled data to be either an output of the first sampling circuit or an output of the second sampling circuit.