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1. (WO2017039846) INTEGRATED CIRCUIT WITH REDUCED ROUTING CONGESTION

Pub. No.:    WO/2017/039846    International Application No.:    PCT/US2016/042352
Publication Date: Fri Mar 10 00:59:59 CET 2017 International Filing Date: Fri Jul 15 01:59:59 CEST 2016
IPC: G06F 17/50
H01L 27/118
Applicants: QUALCOMM INCORPORATED
Inventors: GUPTA, Vinod
MITTAL, Rajiv
CHOUKSEY, Abhishek
Title: INTEGRATED CIRCUIT WITH REDUCED ROUTING CONGESTION
Abstract:
Systems and methods for reducing routing congestion in an integrated circuit allow an integrated circuit floorplan to be modified, for example, after cell placement and global routing. Modifying the floorplan can avoid delays in time to market for the integrated circuit and can avoid increasing the size of the integrated circuit. Reducing routing congestion includes adding routing congestion reduction regions in cell/routing regions of the floorplan. The routing congestion reduction regions may modify how cells can be placed in the region. The routing congestion reduction regions may also modify how connections can be routed in the region. The routing congestion reduction regions may be a halo region that includes modifying preferred routing directions in regions nears edges of hard macros, a hammerhead region that includes laterally expanding the end of the river routing region, and a corner congestion reduction region for use at corners of hard macros.