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1. (WO2017039784) MEMORY DEVICE WITH MULTI-LAYER CHANNEL AND CHARGE TRAPPING LAYER

Pub. No.:    WO/2017/039784    International Application No.:    PCT/US2016/038229
Publication Date: Fri Mar 10 00:59:59 CET 2017 International Filing Date: Sat Jun 18 01:59:59 CEST 2016
IPC: H01L 27/115
H01L 21/02
H01L 21/3205
H01L 29/792
Applicants: CYPRESS SEMICONDUCTOR CORPORATION
Inventors: ZHANG, Renhua
XUE, Lei
SUGINO, Rinji
Title: MEMORY DEVICE WITH MULTI-LAYER CHANNEL AND CHARGE TRAPPING LAYER
Abstract:
A 3-D/vertical non-volatile (NV) memory device such as 3-D NAND flash memory and fabrication method thereof, the NV memory device includes vertical openings disposed in a stack of alternating stack layers of first stack layers and second stack layers over a wafer, a multi-layer dielectric disposed over an inner sidewall of each opening, a first channel layer disposed over the multi-layer dielectric, and a second channel layer disposed over the first channel layer, in which at least one of the first or second channel layers includes polycrystalline germanium or silicon-germanium.