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1. (WO2017039587) METHODS AND DEVICES INTEGRATING III-N TRANSISTOR CIRCUITRY WITH SI TRANSISTOR CIRCUITRY
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/039587 International Application No.: PCT/US2015/047462
Publication Date: 09.03.2017 International Filing Date: 28.08.2015
IPC:
H01L 29/78 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd. Santa Clara, California 95054, US
Inventors:
DASGUPTA, Sansaptak; US
RADOSAVELIJEVIC, Marko; US
THEN, Han Wui; US
PILLARISETTY, Ravi; US
JUN, Kimin; US
MORROW, Patrick; US
RAO, Valluri R.; US
FISCHER, Paul B.; US
CHAU, Robert S.; US
Agent:
HOWARD, James M.; US
Priority Data:
Title (EN) METHODS AND DEVICES INTEGRATING III-N TRANSISTOR CIRCUITRY WITH SI TRANSISTOR CIRCUITRY
(FR) PROCÉDÉS ET DISPOSITIFS INTÉGRANT DES CIRCUITS À TRANSISTORS À BASE DE III-N AVEC DES CIRCUITS À TRANSISTORS À BASE DE SI
Abstract:
(EN) Methods and devices integrating circuitry including both III-N (e.g., GaN) transistors and Si-based (e.g., Si or SiGe) transistors. In some monolithic wafer-level integration embodiments, a silicon-on-insulator (SOI) substrate is employed as an epitaxial platform providing a first silicon surface advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N transistors (e.g., III-N HFETs) are formed, and a second silicon surface advantageous for seeding an epitaxial raised silicon upon which Si-based transistors (e.g., Si FETs) are formed. In some heterogeneous wafer-level integration embodiments, an SOI substrate is employed for a layer transfer of silicon suitable for fabricating the Si-based transistors onto another substrate upon which III-N transistors have been formed. In some such embodiments, the silicon layer transfer is stacked upon a planar interlayer dielectric (ILD) disposed over one or more metallization level interconnecting a plurality of III-N HFETs into HFET circuitry.
(FR) L'invention concerne des procédés et des dispositifs intégrant des circuits comprenant à la fois des transistors à base de III-N (par exemple, GaN) et des transistors à base de Si (par exemple, Si ou SiGe). Dans certains modes de réalisation d'intégration au niveau de la tranche monolithique, un substrat silicium sur isolant (SOI) est utilisé en tant que plate-forme épitaxiale formant une première surface de silicium avantageuse pour ensemencer un empilement de semi-conducteurs III-N épitaxiaux sur lequel sont formés des transistors à base de III-N (par exemple, des HFET à base de III-N), et une seconde surface de silicium avantageuse pour ensemencer du silicium surélevé épitaxial sur lequel sont formés des transistors à base de Si (par exemple, des TEC à base de Si). Dans certains modes de mise en œuvre d'intégration au niveau de la tranche hétérogène, un substrat SOI est utilisé pour un transfert de couche de silicium approprié pour la fabrication des transistors à base de Si sur un autre substrat sur lequel ont été formés des transistors à base de III-N. Dans certains de ces modes de réalisation, le transfert de la couche de silicium est empilé sur un diélectrique intercouche (ILD) plan disposé sur un ou plusieurs niveaux de métallisation interconnectant une pluralité de HFET III-N dans des circuits HFET.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)