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1. (WO2017039581) MICROELECTRONIC PACKAGES WITH HIGH INTEGRATION MICROELECTRONIC DICE STACK
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/039581 International Application No.: PCT/US2015/047420
Publication Date: 09.03.2017 International Filing Date: 28.08.2015
IPC:
H01L 25/065 (2006.01) ,H01L 23/48 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
Applicants:
INTEL IP CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
PATTEN, Richard; DE
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) MICROELECTRONIC PACKAGES WITH HIGH INTEGRATION MICROELECTRONIC DICE STACK
(FR) BOÎTIERS MICRO-ÉLECTRONIQUES AVEC PILE DE MATRICES MICRO-ÉLECTRONIQUES À HAUTE INTÉGRATION
Abstract:
(EN) A microelectronic package may include stacked microelectronic dice, wherein a first microelectronic die is attached to a microelectronic substrate, and a second microelectronic die is stacked over at least a portion of the first microelectronic die, wherein the microelectronic substrate includes a plurality of pillars extending therefrom, wherein the second microelectronic die includes a plurality of pillars extending therefrom in a mirror-image configuration to the plurality of microelectronic substrate pillars, and wherein the second microelectronic die pillars are attached to microelectronic substrate pillars with an attachment material.
(FR) L'invention concerne un boîtier micro-électronique pouvant comprendre des matrices micro-électroniques empilées, une première matrice micro-électronique étant fixée sur un substrat micro-électronique et une seconde matrice micro-électronique étant empilée sur au moins une partie de la première matrice micro-électronique, le substrat micro-électronique comprenant une pluralité de piliers s'étendant depuis celui-ci, la seconde matrice micro-électronique comprenant une pluralité de piliers s'étendant depuis celle-ci dans une configuration en image miroir par rapport à la pluralité de piliers de substrat micro-électronique et les piliers de la seconde matrice micro-électronique étant fixés aux piliers de substrat micro-électronique avec un matériau de fixation.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)