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1. (WO2017039542) METHOD OF ENCAPSULATING A SUBSTRATE
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Pub. No.: WO/2017/039542 International Application No.: PCT/SG2016/050423
Publication Date: 09.03.2017 International Filing Date: 31.08.2016
IPC:
H01L 21/00 (2006.01) ,H01L 27/00 (2006.01) ,H01L 29/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
Applicants:
NANYANG TECHNOLOGICAL UNIVERSITY [SG/SG]; 50 Nanyang Avenue Singapore 639798, SG
MASSACHUSETTS INSTITUTE OF TECHNOLOGY [US/US]; 77 Massachusetts Avenue, Cambridge, Massachusetts 02139, US
Inventors:
LEE, Kwang Hong; SG
LEE, Eng Kian, Kenneth; SG
TAN, Chuan Seng; SG
FITZGERALD, Eugene A.; US
NGUYEN, Viet Cuong; SG
Agent:
FOO, Chee Hiong, Ricky; SG
Priority Data:
62/283,64804.09.2015US
Title (EN) METHOD OF ENCAPSULATING A SUBSTRATE
(FR) PROCÉDÉ D'ENCAPSULATION DE SUBSTRAT
Abstract:
(EN) A method (200) of encapsulating a substrate (202) is disclosed, in which the substrate has at least the following layers: a CMOS device layer (204), a layer of first semiconductor material (206) different to silicon, and a layer of second semiconductor material (208), the layer of first semiconductor material arranged intermediate the CMOS device layer and the layer of second semiconductor material. The method comprises: (i) circumferentially removing (252) a portion of the substrate at the edges; and (ii) depositing (254) a dielectric material on the substrate to replace the portion removed at step (i) for encapsulating at least the CMOS device layer and the layer of first semiconductor material. A related substrate is also disclosed.
(FR) L'invention concerne un procédé (200) d'encapsulation d'un substrat (202), dans lequel le substrat présente au moins les couches suivantes : une couche de dispositif CMOS (204), une couche d'un premier matériau semi-conducteur (206) différent du silicium, et une couche d'un second matériau semi-conducteur (208), la couche de premier matériau semi-conducteur étant agencée entre la couche de dispositif CMOS et la couche de second matériau semi-conducteur. Le procédé consiste à : (i) éliminer de manière circonférentielle (252) une partie du substrat au niveau des bords; et (ii) déposer (254) un matériau diélectrique sur le substrat pour remplacer la partie éliminée à l'étape (i) pour encapsuler au moins la couche de dispositif CMOS et la couche de premier matériau semi-conducteur. L'invention concerne également un substrat correspondant.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)