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1. (WO2017039306) SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SAME
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Pub. No.: WO/2017/039306 International Application No.: PCT/KR2016/009708
Publication Date: 09.03.2017 International Filing Date: 31.08.2016
IPC:
H01L 25/065 (2006.01) ,H01L 23/28 (2006.01) ,H01L 23/00 (2006.01) ,H01L 23/495 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
495
Lead-frames
Applicants:
주식회사 네패스 NEPES CO., LTD. [KR/KR]; 충청북도 음성군 삼성면, 금일로965번길, 105 105, Geumil-ro 965beon-gil, Samseong-myeon Eumseong-gun Chungcheongbuk-do 27651, KR
Inventors:
권용태 KWON, Yong Tae; KR
이준규 LEE, Jun Kyu; KR
Agent:
특허법인 세림 SELIM INTELLECTUAL PROPERTY LAW FIRM; 서울시 서초구 강남대로, 285 태우빌딩, 10층과 11층 10F and 11F, Taewoo Bldg. 285, Gangnam-daero Seocho-gu Seoul 06729, KR
Priority Data:
10-2015-012544304.09.2015KR
Title (EN) SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SAME
(FR) BOÎTIER DE SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(KO) 반도체 패키지 및 그 제조방법
Abstract:
(EN) Disclosed are a wire bond-type semiconductor package, which has a fanout metal pattern formed thereon, and a method for manufacturing the same. A semiconductor package according to an embodiment of the present invention comprises: a frame, which is configured such that an electric signal can be transferred between upper and lower portions thereof, and which has a penetrating portion formed therein; a first semiconductor chip contained in the penetrating portion of the frame; a second semiconductor chip mounted on the first semiconductor chip; a wire that electrically connects the first semiconductor chip and a signal unit of the frame; a sealing material that molds the frame, the first semiconductor chip, the second semiconductor chip, and the wire such that the same are integrated; and a wiring unit provided beneath the frame and the first semiconductor chip and electrically connected to the frame.
(FR) L'invention concerne un boîtier de semi-conducteur du type à connexion par fils, sur lequel est formé un motif métallique de sortance, et son procédé de fabrication. Un boîtier de semi-conducteur selon un mode de réalisation de la présente invention comprend : un cadre, qui est configuré de manière qu'un signal électrique puisse être transféré entre ses parties supérieure et inférieure, et ayant une partie pénétrante disposée en son sein ; une première puce de semi-conducteur contenue dans la partie pénétrante du cadre ; une seconde puce de semi-conducteur montée sur la première puce de semi-conducteur ; un fil qui connecte électriquement la première puce de semi-conducteur et une unité de signal du cadre ; un matériau d'étanchéité qui moule le cadre, la première puce de semi-conducteur, la seconde puce de semi-conducteur et le fil de manière à les intégrer ; et une unité de câblage se trouvant sous le cadre et la première puce de semi-conducteur et connectée électriquement au cadre.
(KO) 팬아웃 금속 패턴이 형성된 와이어 본드형 반도체 패키지 및 이의 제조방법이 개시된다. 본 발명의 실시예에 따른 반도체 패키지는 상부와 하부 사이에 전기적 신호의 전달이 가능하고 관통부가 형성되는 프레임과, 프레임의 관통부에 수용되는 제1 반도체 칩과, 제1 반도체 칩 상에 탑재되는 제2 반도체 칩과, 제1 반도체 칩과 프레임의 신호부를 전기적으로 연결하는 와이어와, 프레임과 제1 반도체 칩과 제2 반도체 칩과 와이어를 일체화하도록 몰딩하는 봉지재와, 프레임과 제1 반도체 칩의 하부에 마련되고 프레임과 전기적으로 연결되는 배선부를 포함한다.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)