Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2017039275) SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2017/039275 International Application No.: PCT/KR2016/009634
Publication Date: 09.03.2017 International Filing Date: 30.08.2016
IPC:
H01L 23/367 (2006.01) ,H01L 23/488 (2006.01) ,H01L 23/40 (2006.01) ,H01L 23/373 (2006.01) ,H01L 23/48 (2006.01)
[IPC code unknown for H01L 23/367][IPC code unknown for H01L 23/488][IPC code unknown for H01L 23/40][IPC code unknown for H01L 23/373][IPC code unknown for H01L 23/48]
Applicants:
삼성전자 주식회사 SAMSUNG ELECTRONICS CO., LTD. [KR/KR]; 경기도 수원시 영통구 삼성로 129 129, Samsung-ro, Yeongtong-gu Suwon-si Gyeonggi-do 16677, KR
Inventors:
김영호 KIM, Youngho; KR
박환필 PARK, Hwanpil; KR
Agent:
특허법인 고려 KORYO IP & LAW; KR
Priority Data:
10-2015-012316631.08.2015KR
10-2016-010674423.08.2016KR
Title (EN) SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME
(FR) STRUCTURE DE BOÎTIER DE SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(KO) 반도체 패키지 구조체, 및 그 제조 방법
Abstract:
(EN) A method for manufacturing a semiconductor package is provided. The present invention may comprise: a base substrate; a die, which is arranged on the base substrate, and which comprises a semiconductor element; a solder bump arranged on one surface of the die so as to discharge heat, which has been generated by the die, to the outside; and a solder ball arranged on the other surface of the die, which lies opposite the one surface thereof, so as to transmit a signal, which has been generated by the semiconductor element of the die, to an external device.
(FR) L'invention concerne un procédé de fabrication d'un boîtier de semi-conducteur. La présente invention peut comprendre : un substrat de base; une puce, qui est disposée sur le substrat de base, et qui comprend un élément à semi-conducteur; une bosse de soudure disposée sur une surface de la puce de manière à évacuer à l'extérieur de la chaleur qui a été générée par la puce; et une bille de soudure disposée sur l'autre surface de la puce, qui se trouve à l'opposé de sa surface susmentionnée, de manière à transmettre à un dispositif externe un signal qui a été généré par l'élément à semi-conducteur de la puce.
(KO) 반도체 패키지 구조체의 제조 방법이 제공된다. 베이스 기판, 상기 베이스 기판 상에 배치되며, 반도체 소자를 포함하는 다이(die), 상기 다이의 일면 상에 배치되고, 상기 다이에서 생성된 열을 외부로 방출하는 솔더 범프(solder bump) 및 상기 다이의 상기 일면에 대향하는 타면 상에 배치되고, 상기 다이의 상기 반도체 소자에서 생성된 신호를 외부 장치로 전송하는 솔더 볼(solder ball)을 포함하여 이루어질 수 있다.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)