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1. (WO2017038582) PACKAGE FOR HOUSING SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR DEVICE

Pub. No.:    WO/2017/038582    International Application No.:    PCT/JP2016/074664
Publication Date: Fri Mar 10 00:59:59 CET 2017 International Filing Date: Thu Aug 25 01:59:59 CEST 2016
IPC: H01L 23/02
H01L 23/04
H01L 31/02
H01S 5/022
Applicants: KYOCERA CORPORATION
京セラ株式会社
Inventors: ASANO, Toshimitsu
浅野 稔弘
Title: PACKAGE FOR HOUSING SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR DEVICE
Abstract:
The peripheral walls of this package for housing a semiconductor element consist of a first wall, a second wall, a third wall, and a fourth wall. The first wall is provided with a first fitting section, a second fitting section, and a through-hole. The second wall faces the first wall. The third wall is adjacent to the first wall and the second wall. On the third wall, a third fitting section that fits with the first fitting section is provided to a third end section, and a fourth end section is integrally connected to the second wall. On the fourth wall, a fourth fitting section that fits with the second fitting section is provided to a fifth end section, and a sixth end section is integrally connected to the second wall.