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1. (WO2017038110) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/038110 International Application No.: PCT/JP2016/053796
Publication Date: 09.03.2017 International Filing Date: 09.02.2016
IPC:
H01L 23/12 (2006.01) ,H05K 3/10 (2006.01) ,H05K 3/46 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
10
in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
Applicants:
日立化成株式会社 HITACHI CHEMICAL COMPANY, LTD. [JP/JP]; 東京都千代田区丸の内一丁目9番2号 9-2, Marunouchi 1-chome, Chiyoda-ku, Tokyo 1006606, JP
Inventors:
満倉 一行 MITSUKURA Kazuyuki; JP
鳥羽 正也 TOBA Masaya; JP
岩下 健一 IWASHITA Kenichi; JP
浦島 航介 URASHIMA Kohsuke; JP
蔵渕 和彦 KURAFUCHI Kazuhiko; JP
Agent:
長谷川 芳樹 HASEGAWA Yoshiki; JP
Priority Data:
2015-16978228.08.2015JP
2015-16978328.08.2015JP
Title (EN) SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置及びその製造方法
Abstract:
(EN) Provided is a method for manufacturing, at an excellent yield and a low cost, a high-density semiconductor device wherein excellent transmission between chips is performed. The method for manufacturing the semiconductor device is provided with: an insulating layer forming step for forming an insulating layer 3 on a substrate 1, said insulating layer having a trench section 4; a copper layer forming step for forming a copper layer 5a on the insulating layer 3 such that the trench section 4 is buried; and a removing step for removing, using a fly cut method, the copper layer 5a on the insulating layer 3 by leaving a copper layer portion in the trench section 4.
(FR) L'invention concerne un procédé de fabrication, à un excellent rendement et à un faible coût, d'un dispositif à semi-conducteur à haute densité, une excellente transmission entre puces étant effectuée. Le procédé de fabrication du dispositif à semi-conducteur est pourvu : d'une étape de formation de couche isolante consistant à former une couche isolante 3 sur un substrat 1, ladite couche isolante ayant une section de tranchée 4 ; d'une étape de formation de couche de cuivre consistant à former une couche de cuivre 5a sur la couche isolante 3 de telle sorte que la section de tranchée 4 est enterrée ; et d'une étape de retrait consistant à retirer, à l'aide d'un procédé de découpe volante, la couche de cuivre 5a sur la couche isolante 3 en laissant une partie de couche de cuivre dans la section de tranchée 4.
(JA)  チップ同士の伝送に優れた高密度の半導体装置を良好な歩留まり、かつ低コストで製造できる製造方法を提供する。半導体装置の製造方法は、溝部4を有する絶縁層3を基板1上に形成する絶縁層形成工程と、溝部4を埋めるように絶縁層3上に銅層5aを形成する銅層形成工程と、溝部4内の銅層部分を残し、絶縁層3上の銅層5aをフライカット法により除去する除去工程と、を備える。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)