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1. (WO2017038095) PROGRAMMABLE LOGIC INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE, AND CHARACTERIZATION METHOD

Pub. No.:    WO/2017/038095    International Application No.:    PCT/JP2016/003979
Publication Date: Fri Mar 10 00:59:59 CET 2017 International Filing Date: Thu Sep 01 01:59:59 CEST 2016
IPC: H01L 21/82
G06F 17/50
H01L 27/105
H01L 45/00
H01L 49/00
H03K 19/177
Applicants: NEC CORPORATION
日本電気株式会社
Inventors: TADA, Ayuka
多田 あゆ香
SAKIMURA, Noboru
崎村 昇
MIYAMURA, Makoto
宮村 信
TSUJI, Yukihide
辻 幸秀
NEBASHI, Ryusuke
根橋 竜介
BAI, Xu
白 旭
SAKAMOTO, Toshitsugu
阪本 利司
Title: PROGRAMMABLE LOGIC INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE, AND CHARACTERIZATION METHOD
Abstract:
The purpose of the present invention is to provide a method for efficiently performing characterization of a programmable logic integrated circuit having a crossbar switch involving the use of a resistance change element, in order to perform circuit verification using static timing analysis. This programmable logic integrated circuit has a crossbar switch having a resistance change element and a logic circuit logically configured using the crossbar switch, wherein the programmable logic integrated circuit is divided into a plurality of leaf cells having a plurality of load circuits that have a portion of the crossbar switch and a power source element for inputting into the crossbar switch, the leaf cells are split into delay paths having a base leaf cell and a correction leaf cell, and circuits are verified on the basis of a delay information library in which the delay time of the base leaf cells and the correction delay for the correction leaf cells are integrated to obtain the delay time for the leaf cells.