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1. (WO2017037880) ΔΣ MODULATOR, TRANSMITTER, AND INTEGRATOR
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/037880 International Application No.: PCT/JP2015/074893
Publication Date: 09.03.2017 International Filing Date: 01.09.2015
IPC:
H03M 7/32 (2006.01) ,G06F 7/544 (2006.01) ,G06F 17/10 (2006.01) ,H03M 3/02 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
7
Conversion of a code where information is represented by a given sequence or number of digits to a code where the same information is represented by a different sequence or number of digits
30
Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
32
Conversion to or from delta modulation, i.e. one-bit differential modulation
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
7
Methods or arrangements for processing data by operating upon the order or content of the data handled
38
Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48
using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
544
for evaluating functions by calculation
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
17
Digital computing or data processing equipment or methods, specially adapted for specific functions
10
Complex mathematical operations
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
M
CODING, DECODING OR CODE CONVERSION, IN GENERAL
3
Conversion of analogue values to or from differential modulation
02
Delta modulation, i.e. one-bit differential modulation
Applicants:
日本電気株式会社 NEC CORPORATION [JP/JP]; 東京都港区芝五丁目7番1号 7-1, Shiba 5-chome, Minato-ku, Tokyo 1088001, JP
Inventors:
谷尾 真明 TANIO Masaaki; JP
山瀬 知行 YAMASE Tomoyuki; JP
堀 真一 HORI Shinichi; JP
Agent:
棚井 澄雄 TANAI Sumio; JP
Priority Data:
Title (EN) ΔΣ MODULATOR, TRANSMITTER, AND INTEGRATOR
(FR) MODULATEUR ΔΣ, ÉMETTEUR ET INTÉGRATEUR
(JA) ΔΣ変調器、送信機及び積分器
Abstract:
(EN) This ΔΣ modulator uses multiple integrators. The integrators each: include multiple stages of adder sequences each formed of multiple serially-connected adders; feedback, as inputs to a first adder sequence which is the first stage of the multiple stages, a result from a second adder sequence which is the last stage of the multiple stages; process the inputs supplied to the multiple adders of the first adder sequence; and supply the inputs to the second adder sequence.
(FR) L'invention concerne un modulateur ΔΣ qui utilise de multiples intégrateurs. Chacun des intégrateurs : comprend de multiples étages de séquences d'additionneurs formées chacune de multiples additionneurs connectés en série ; renvoie, en tant qu'entrées dans une première séquence d'additionneurs qui est le premier étage des multiples étages, un résultat provenant d'une deuxième séquence d'additionneurs qui est le dernier étage des multiples étages ; traite les entrées fournies aux multiples additionneurs de la première séquence d'additionneurs ; fournit les entrées à la deuxième séquence d'additionneurs.
(JA) このΔΣ変調器は、複数の積分器を用いたΔΣ変調器であって、前記積分器は、それぞれ直列に接続された複数のアダーからなるアダー列を複数段備え、前記複数段の初段である第一のアダー列の入力として前記複数段の最終段である第二のアダー列の結果をフィードバックし、前記第一のアダー列の複数のアダーへ供給される入力を処理して前記第二のアダー列に供給する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)