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1. (WO2017036113) PIPELINE MULTIPLEXER LOOP ARCHITECTURE FOR DECISION FEEDBACK EQUALIZER CIRCUITS

Pub. No.:    WO/2017/036113    International Application No.:    PCT/CN2016/076076
Publication Date: Fri Mar 10 00:59:59 CET 2017 International Filing Date: Fri Mar 11 00:59:59 CET 2016
IPC: G11C 7/02
H04L 25/03
Applicants: HUAWEI TECHNOLOGIES CO., LTD.
Inventors: HO, Huong
Title: PIPELINE MULTIPLEXER LOOP ARCHITECTURE FOR DECISION FEEDBACK EQUALIZER CIRCUITS
Abstract:
Circuits (300, 400), devices, methods for decision feedback equalization are described. A decision feedback circuit (300) can include a plurality of decision feedback equalizer (DFE) branches, each DFE branch including: a pre-computation stage (305) configured to generate a set of tap-adjusted inputs, each tap-adjusted input corresponding to a possible value of a previous output for the same DFE branch; and a decision feedback stage (306) comprising a multiplexer circuit configured to select at least one output from the set of tap-adjusted inputs based on tap-adjusted inputs from other DFE branches. For at least a first DFE branch of the plurality of DFE branches, at least one selection line for the multiplexer circuit in the decision feedback stage (306) of at least the first DFE branch of the plurality of DFE branches is an intermediate value from a multiplexer circuit for a second DFE branch of the plurality of DFE branches.