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1. (WO2017035510) INTEGRATED CIRCUIT (IC) PACKAGE COMPRISING ELECTROSTATIC DISCHARGE (ESD) PROTECTION
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Pub. No.: WO/2017/035510 International Application No.: PCT/US2016/049123
Publication Date: 02.03.2017 International Filing Date: 26.08.2016
IPC:
H01L 23/60 (2006.01) ,H01L 23/62 (2006.01) ,H01L 23/48 (2006.01) ,H01L 27/02 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
60
Protection against electrostatic charges or discharges, e.g. Faraday shields
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
62
Protection against overcurrent or overload, e.g. fuses, shunts
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
Applicants:
QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
GU, Shiqun; US
WORLEY, Eugene Robert; US
RADOJCIC, Ratibor; US
RAY, Urmi; US
Agent:
THAVONEKHAM, S. Sean; US
Priority Data:
14/838,03427.08.2015US
Title (EN) INTEGRATED CIRCUIT (IC) PACKAGE COMPRISING ELECTROSTATIC DISCHARGE (ESD) PROTECTION
(FR) BOÎTIER DE CIRCUIT INTÉGRÉ (IC) COMPRENANT UNE PROTECTION CONTRE LES DÉCHARGES ÉLECTROSTATIQUES (ESD)
Abstract:
(EN) An integrated circuit (IC) package includes a die, a package substrate coupled to the die, and a first electrostatic discharge (ESD) protection component coupled to the package substrate, where the first electrostatic discharge (ESD) protection component is configured to provide package level electrostatic discharge (ESD) protection. In some implementations, the first electrostatic discharge (ESD) protection component is embedded in the package substrate. In some implementations, the die includes an internal electrostatic discharge (ESD) protection component configured to provide die level electrostatic discharge (ESD) protection. In some implementations, the internal electrostatic discharge (ESD) protection component and the first electrostatic discharge (ESD) protection component are configured to provide cumulative electrostatic discharge (ESD) protection for the die.
(FR) L'invention concerne un boîtier de circuit intégré (IC) comprenant une puce, un substrat de boîtier couplé à la puce, et un premier élément de protection contre les décharges électrostatiques (ESD) couplé au substrat du boîtier, ce premier élément de protection contre les décharges électrostatiques (ESD) étant conçu pour fournir une protection contre les décharges électrostatiques (ESD) au niveau du boîtier. Dans certains modes de réalisation, le premier élément de protection contre les décharges électrostatiques (ESD) est intégré dans le substrat de boîtier. Dans certains modes de réalisation, la puce comprend un élément interne de protection contre les décharges électrostatiques (ESD) conçu pour fournir une protection contre les décharges électrostatiques (ESD) au niveau de la puce. Dans certains modes de réalisation, l'élément interne de protection contre les décharges électrostatiques (ESD) et le premier élément de protection contre les décharges électrostatiques (ESD) sont conçus pour fournir une protection cumulative contre les décharges électrostatiques (ESD) pour la puce.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)