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1. (WO2017034864) BACK-SIDE ILLUMINATED PIXELS WITH INTERCONNECT LAYERS
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/034864 International Application No.: PCT/US2016/047207
Publication Date: 02.03.2017 International Filing Date: 16.08.2016
IPC:
H01L 27/146 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
Applicants:
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC [US/US]; 5005 E. McDowell Road MD A700 Phoenix, Arizona 85008, US
Inventors:
VELICHKO, Sergey; US
SILSBY, Christopher; US
Agent:
ANDERSON, Daniel J.; US
TUTTLE, Robert M.; US
ENGEL, Joshua D.; US
Priority Data:
14/836,59926.08.2015US
Title (EN) BACK-SIDE ILLUMINATED PIXELS WITH INTERCONNECT LAYERS
(FR) PIXELS ÉCLAIRÉS PAR L'ARRIÈRE COMPRENANT COUCHES D'INTERCONNEXION
Abstract:
(EN) An imaging pixel (100) may be provided with an upper substrate layer (30), a lower substrate layer (32), a floating diffusion region (52) in the upper substrate layer, and a photodiode (36) in the upper substrate layer that is coupled to the floating diffusion region. The imaging pixel may also include a source follower transistor (62) in the lower substrate layer and an interconnect layer (34) in between the upper substrate layer and the lower substrate layer. The interconnect layer may couple the floating diffusion region directly to the source follower transistor. The imaging pixel may include a reset transistor (54) in the upper substrate layer. The imaging pixel may include a metal layer (58) in the lower substrate layer, a transfer transistor (50) in the upper substrate layer, and an interconnect layer (34-2) that couples the transfer transistor to the metal layer.
(FR) L'invention concerne un pixel d'imagerie (100) qui peut être pourvu d'une couche de substrat supérieure (30), d'une couche de substrat inférieure (32), d'une zone de diffusion flottante (52) dans la couche de substrat supérieure, et d'une photodiode (36) dans la couche de substrat supérieure qui est couplée à la zone de diffusion flottante. Le pixel d'imagerie peut également comprendre un transistor à source suiveuse (62) dans la couche de substrat inférieure, et une couche d'interconnexion (34) entre la couche de substrat supérieure et la couche de substrat inférieure. La couche d'interconnexion peut coupler la zone de diffusion flottante directement au transistor à source suiveuse. Le pixel d'imagerie peut comprendre un transistor de réinitialisation (54) dans la couche de substrat supérieure. Le pixel d'imagerie peut comprendre une couche métallique (58) dans la couche de substrat inférieure, un transistor de transfert (50) dans la couche de substrat supérieure, et une couche d'interconnexion (34-2) qui couple le transistor de transfert à la couche métallique.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)