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1. (WO2017034754) EFFICIENT ENCODING AND DECODING ARCHITECTURE FOR HIGH-RATE DATA TRANSFER THROUGH A PARALLEL BUS

Pub. No.:    WO/2017/034754    International Application No.:    PCT/US2016/044592
Publication Date: Fri Mar 03 00:59:59 CET 2017 International Filing Date: Fri Jul 29 01:59:59 CEST 2016
IPC: G06F 13/42
Applicants: QUALCOMM INCORPORATED
Inventors: KUDEKAR, Shrinivas
NIESEN, Urs
Title: EFFICIENT ENCODING AND DECODING ARCHITECTURE FOR HIGH-RATE DATA TRANSFER THROUGH A PARALLEL BUS
Abstract:
System, methods, and apparatus are described that facilitate transmission/reception of data over a multi-line parallel bus. In an example, the apparatus selects from a sequential series of data bits a plurality of data bits for transmission over a plurality of parallel bus lines. For each bus line of the plurality of parallel bus lines, the apparatus compares a state of a current data bit selected for transmission on a current bus line during a current clock cycle with one or more conditions related to the current bus line or at least one bus line adjacent to the current bus line, wherein the one or more conditions includes a state of two data bits respectively transmitted on two bus lines adjacent to the current bus line during a previous clock cycle, and determines whether to transmit the current data bit on the current bus line based on the comparison.