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1. (WO2017034711) APPARATUS AND METHOD TO REDUCE POWER LOSSES IN AN INTEGRATED VOLTAGE REGULATOR

Pub. No.:    WO/2017/034711    International Application No.:    PCT/US2016/043183
Publication Date: Fri Mar 03 00:59:59 CET 2017 International Filing Date: Thu Jul 21 01:59:59 CEST 2016
IPC: H02M 3/158
H02M 1/08
H02M 1/00
Applicants: INTEL CORPORATION
Inventors: BHARATH, Krishna
VENKATARAMAN, Srikrishnan
LAMBERT, William J.
HILL, Michael J.
SLEPOY, Alexander
ZHONG, Dong
RADHAKRISHNAN, Kaladhar
AGUIRRE DIAZ, Hector A.
DOUGLAS, Jonathan P.
Title: APPARATUS AND METHOD TO REDUCE POWER LOSSES IN AN INTEGRATED VOLTAGE REGULATOR
Abstract:
Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.