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1. (WO2017034647) MULTI TIER THREE-DIMENSIONAL MEMORY DEVICES INCLUDING VERTICALLY SHARED BIT LINES

Pub. No.:    WO/2017/034647    International Application No.:    PCT/US2016/036724
Publication Date: Fri Mar 03 00:59:59 CET 2017 International Filing Date: Fri Jun 10 01:59:59 CEST 2016
IPC: H01L 27/115
Applicants: SANDISK TECHNOLOGIES LLC
Inventors: LU, Zhenyu
CHIEN, Henry
ALSMEIER, Johann
MIYATA, Koji
ZHANG, Tong
MUI, Man
KAI, James
SHI, Wenguang
WEI, Zhao
HU, Xiaolong
XU, Jiyin
HEMINK, Gerrit Jan
PETTI, Christopher
Title: MULTI TIER THREE-DIMENSIONAL MEMORY DEVICES INCLUDING VERTICALLY SHARED BIT LINES
Abstract:
A multi-tier memory device is formed over a substrate such that memory stack structures extend through an alternating stack of insulating layers and electrically conductive layers within each tier. Bit lines are formed between an underlying tier having drain regions over semiconductor channels and an overlying tier having drain regions under semiconductor channel, such that the bit lines are shared between the underlying tier and the overlying tier. Source lines can be formed over each tier in which source regions overlie semiconductor channels and drain regions. If another tier is present above the source lines, the source lines can be shared between two vertically neighboring tiers.